ADUC812BS ,MicroConverter/ Multichannel 12-Bit ADC with Embedded FLASH MCUSPECIFICATIONS3, 4DC ACCURACYResolution 12 12 BitsIntegral Nonlinearity ±1/2 ±1/2 LSB typ f = 100 k ..
ADUC812BSZ-REEL , MicroConverter, Multichannel 12-Bit ADC with Embedded Flash MCU
ADUC812BSZ-REEL , MicroConverter, Multichannel 12-Bit ADC with Embedded Flash MCU
ADUC814ARU ,Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 8kB Flash + 6-Ch 12-Bit ADC + Dual 12-Bit DACOverview........ 21 Programming a Byte........ 33 ADC Transfer Function....... 21 User Interface to ..
ADUC814ARUZ , MicroConverter®, Small Package 12-Bit ADC with Embedded Flash MCU
ADUC814BRU ,MicroConverter/ Small Package 12-Bit ADC with Embedded Flash MCUOverview........ 21 Programming a Byte........ 33 ADC Transfer Function....... 21 User Interface to ..
AM2732B-305DC , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2732B-305DI , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2732B-455DC , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2732B-455DI , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM27512 , 65,536x8-Bit UV Erasable PROM
AM27512-25DC , 65,536x8-Bit UV Erasable PROM
ADUC812BS
MicroConverter/ Multichannel 12-Bit ADC with Embedded FLASH MCU
REV. 0
MicroConverter™, Multichannel
12-Bit ADC with Embedded FLASH MCU
FUNCTIONAL BLOCK DIAGRAM
FEATURES
ANALOG I/O
8-Channel, High Accuracy 12-Bit ADC
On-Chip, 40 ppm/�C Voltage Reference
High Speed 200 kSPS
DMA Controller for High Speed ADC-to-RAM Capture
Two 12-Bit Voltage Output DACs
On-Chip Temperature Sensor Function
MEMORY
8K Bytes On-Chip Flash/EE Program Memory
640 Bytes On-Chip Flash/EE Data Memory
On-Chip Charge Pump (No Ext. VPP Requirements)
256 Bytes On-Chip Data RAM
16M Bytes External Data Address Space
64K Bytes External Program Address Space
8051-COMPATIBLE CORE
12 MHz Nominal Operation (16 MHz Max)
Three 16-Bit Timer/Counters
32 Programmable I/O lines
High Current Drive Capability—Port3
Nine Interrupt Sources, Two Priority Levels
POWER
Specified for 3 V and 5 V Operation
Normal, Idle and Power-Down Modes
ON-CHIP PERIPHERALS
UART Serial I/O
2-Wire (I2C®-Compatible) and SPI® Serial I/O
Watchdog Timer
Power Supply Monitor
APPLICATIONS
Intelligent Sensors (IEEE 1451.2-Compatible)
Battery Powered Systems (Portable PCs, Instruments,
Monitors)
Transient Capture Systems
DAS and Communications Systems
GENERAL DESCRIPTIONThe ADuC812 is a fully integrated 12-bit data acquisition
system incorporating a high performance self-calibrating
multichannel ADC, two 12-bit DACs and programmable 8-bit
(8051-compatible) MCU on a single chip.
The programmable 8051-compatible core is supported by
8K bytes Flash/EE program memory, 640 bytes Flash/EE data
memory and 256 bytes data SRAM on-chip.
Additional MCU support functions include Watchdog Timer,
Power Supply Monitor and ADC DMA functions. 32 Program-
mable I/O lines, I2C-compatible, SPI and Standard UART
Serial Port I/O are provided for multiprocessor interfaces and
I/O expansion.
Normal, idle and power-down operating modes for both the
MCU core and analog converters allow for flexible power man-
agement schemes suited to low power applications. The part is
specified for 3 V and 5 V operation over the industrial tempera-
ture range and is available in a 52-lead, plastic quad flatpack
package.2C is a registered trademark of Philips Corporation.
MicroConverter is a trademark of Analog Devices, Inc.
SPI is a registered trademark of Motorola Inc.
ADuC812–SPECIFICATIONS1, 2(AVDD = DVDD = +3.0 V or +5.0 V � 10%, VREF = 2.5 V Internal Reference,
MCLKIN = 16.0 MHz, DAC VOUT Load to AGND; RL = 10 k�, CL = 100 pF. All specifications TA = TMIN to TMAX, unless otherwise noted.)
ADuC812
ADuC812–SPECIFICATIONS1, 2NOTESSpecifications apply after calibration.Temperature range –40°C to +85°C.Linearity is guaranteed during normal MicroConverter Core operation.Linearity may degrade when programming or erasing the 640 Byte Flash/EE space during ADC conversion times due to on-chip charge pump activity.Measured in production at VDD = 5 V after Software Calibration Routine at +25°C only.User may need to execute Software Calibration Routine to achieve these specifications, which are configuration dependent.The offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADuC812 can compensate.SNR calculation includes distortion and noise components.The temperature sensor will give a measure of the die temperature directly, air temperature can be inferred from this result.DAC linearity is calculated using:
reduced code range of 48 to 4095, 0 to VREF range
reduced code range of 48 to 3995, 0 to VDD range
DAC output load = 10 kΩ and 50 pF.Flash/EE Memory Performance Specifications are qualified as per JEDEC Specification A103 (Data Retention) and JEDEC Draft Specification All7 (Endurance).Endurance Cycling is evaluated under the following conditions:
Mode= Byte Programming, Page Erase Cycling
Cycle Pattern= 00Hex to FFHex
Erase Time= 20 ms
Program Time= 100 µsIDD at other MCLKIN frequencies is typically given by:
Normal Mode (VDD = 5 V):IDD = (1.6 × MCLKIN) + 6
Normal Mode (VDD = 3 V):IDD = (0.8 × MCLKIN) + 3
Idle Mode (VDD = 5 V):IDD = (0.75 × MCLKIN) + 6
Idle Mode (VDD = 3 V):IDD = (0.25 × MCLKIN) + 3
Where MCLKIN is the oscillator frequency in MHz and resultant IDD values are in mA.IDD Currents are expressed as a summation of analog and digital power supply currents during normal MicroConverter operation.IDD is not measured during Flash/EE program or erase cycles; IDD will typically increase by 10 mA during these cycles.Analog IDD = 2 mA (typ) in normal operation (internal VREF, ADC and DAC peripherals powered on).EA = Port0 = DVDD, XTAL1 (Input) tied to DVDD, during this measurement.
Typical specifications are not production tested, but are supported by characterization data at initial product release.
Specifications subject to change without notice.
Please refer to User Guide, Quick Reference Guide, Application Notes and Silicon Errata Sheet at /microconverter for additional information.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADuC812 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DVDD to DGND, AVDD to AGND . . . . . . . . .–0.3 V to +7 V
Digital Input Voltage to DGND . . . . .–0.3 V, DVDD + 0.3 V
Digital Output Voltage to DGND . . . .–0.3 V, DVDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . .–0.3 V, AVDD + 0.3 V
Analog Inputs to AGND . . . . . . . . . . . .–0.3 V, AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
P0.7/AD7P0.6/AD6P0.5/AD5P0.4/AD4DV
DGNDP0.3/AD3P0.2/AD2P0.1/AD1P0.0/AD0ALEPSENEA
P1.0/ADC0/T2
P1.1/ADC1/T2EX
P1.2/ADC2
P1.3/ADC3
AVDD
AGND
CREF
VREF
DAC0
DAC1
P1.4/ADC4
P1.5/ADC5/SS
P1.6/ADC6
P2.7/A15/A23
P2.6/A14/A22
P2.5/A13/A21
P2.4/A12/A20
DGND
DVDD
XTAL2 (OUTPUT)
XTAL1 (INPUT)
P2.3/A11/A19
P2.2/A10/A18
P2.1/A9/A17
P2.0/A8/A16
SDATA/MOSI
P1.7/ADC7
RESET
P3.0/RxD
P3.1/TxD
P3.2/
INT0
P3.3/
INT1
/MISO
DGND
P3.4/T0
P3.5/T1/
CONVST
P3.7/
SCLOCK
P3.6/
ORDERING GUIDE
QuickStart™ Development SystemEval-ADuC812QS
ADuC812
PIN FUNCTION DESCRIPTIONSAGND
P1.0–P1.7
ADC0–ADC7
T2EX
SDATA
SCLOCK
MOSI
MISO
DAC0
DAC1
RESET
P3.0–P3.7
RxD
TxD
INT0
INT1
CONVST
XTAL2
XTAL1
DGND
P2.0–P2.7
(A8–A15)
(A16–A23)
TERMINOLOGY
ADC SPECIFICATIONS
Integral NonlinearityThis is the maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition and full scale, a point
1/2 LSB above the last code transition.
Differential NonlinearityThis is the difference between the measured and the ideal 1LSB
change between any two adjacent codes in the ADC.
Offset ErrorThis is the deviation of the first code transition (0000...000)
to (0000...001) from the ideal, i.e., +1/2 LSB.
Full-Scale ErrorThis is the deviation of the last code transition from the ideal
AIN voltage (Full Scale – 1.5 LSB) after the offset error has
been adjusted out.
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise +distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic DistortionTotal Harmonic Distortion is the ratio of the rms sum of the
harmonics to the fundamental.
DAC SPECIFICATIONS
Relative AccuracyRelative accuracy or endpoint linearity is a measure of the maxi-
mum deviation from a straight line passing through the end-
points of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error.
Voltage Output Settling TimeThis is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital to Analog Glitch ImpulseThis is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV sec.
ADuC812
ADuC812 ARCHITECTURE, MAIN FEATURESThe ADuC812 is a highly integrated high accuracy 12-bit data
acquisition system. At its core, the ADuC812 incorporates a high
performance 8-bit (8051-Compatible) MCU with on-chip repro-
grammable nonvolatile Flash/EE program memory controlling a
multichannel (8-input channels), 12-bit ADC.
The chip incorporates all secondary functions to fully support the
programmable data acquisition core. These secondary functions
include User Flash/EE Data Memory, Watchdog Timer (WDT),
Power Supply Monitor (PSM) and various industry-standard
parallel and serial interfaces.
ADuC812 MEMORY ORGANIZATIONAs with all 8051-compatible devices, the ADuC812 has separate
address spaces for Program and Data memory as shown in Fig-
ure 1. Also as shown in Figure 1, an additional 640 Bytes of
Flash/EE Data Memory are available to the user. The Flash/EE
Data Memory area is accessed indirectly via a group of control
registers mapped in the Special Function Register (SFR) area.
The lower 128 bytes of internal data memory are mapped as
shown in Figure 2. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 through R7. The next
16 bytes (128 bits) above the register banks form a block of bit
addressable memory space at bit addresses 00H through 7FH.
The SFR space is mapped in the upper 128 bytes of internal
data memory space. The SFR area is accessed by direct address-
ing only and provides an interface between the CPU and all on-
chip peripherals. A block diagram showing the programming
model of the ADuC812 via the SFR area is shown in Figure 3.
Figure 2.Lower 128 Bytes of Internal RAM
Figure 3.ADuC812 Programming Model
ADC CIRCUIT INFORMATION
General OverviewThe ADC conversion block incorporates a 5 µs, 8-channel,
12-bit, single supply A/D converter. This block provides the
user with multichannel mux, track/hold, on-chip reference,
calibration features and A/D converter. All components in this
block are easily configured via a 3-register SFR interface.
Table I.ADCCON1 SFR Bit Designationsprovided on-chip. The internal reference may be overdriven via
the external VREF pin. This external reference can be in the
range 2.3 V to AVDD.
Single step or continuous conversion modes can be initiated in
software or, alternatively, by applying a convert signal to an
external Pin 25 (CONVST). Timer 2 can also be configured
to generate a repetitive trigger for ADC conversions. The ADC
may be configured to operate in a DMA Mode whereby the
ADC block continuously converts and captures samples to an
external RAM space without any interaction from the MCU
core. This automatic capture facility can extend through aMByte external Data Memory space.
The ADuC812 is shipped with factory programmed calibration
coefficients that are automatically downloaded to the ADC on
power-up, ensuring optimum ADC performance. The ADC
core contains internal Offset and Gain calibration registers, a
software calibration routine is provided to allow the user to
overwrite the factory programmed calibration coefficients if
required, thus minimizing the impact of endpoint errors in the
users target system.
A voltage output from an on-chip temperature sensor propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexor (effectively a 9th ADC channel
input) facilitating a temperature sensor implementation.
ADC Transfer FunctionThe analog input range for the ADC is 0 V to VREF. For this
range, the designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight
binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when
VREF = 2.5 V. The ideal input/output transfer characteristic for
the 0 to VREF range is shown in Figure 4.
OUTPUT
CODE
000...0001LSB+FS
–1LSBVOLTAGE INPUTFigure 4.ADuC812 ADC Transfer Function
SFR Interface to ADC BlockThe ADC operation is fully controlled via three SFRs, namely:
ADCCON1 – (ADC Control SFR #1)The ADCCON1 register controls conversion and acquisition
times, hardware conversion modes and power-down modes as
detailed below.
SFR Address:EFH
ADuC812
ADCCON3 – (ADC Control SFR #3)The ADCCON3 register gives user software an indication of
ADC busy status.
SFR Address:F5H
SFR Power On Default Value:00H
Bit Addressable:NO
Table III.ADCCON3 SFR Bit Designations
ADC Internal ReferenceIf the internal reference is being used, both the VREF and CREF
pins should be decoupled with 100 nF capacitors to AGND.
These decoupling capacitors should be placed very close to the
VREF and CREF pins. For specified performance, it is recom-
mended that when using an external reference, this reference
should be between 2.3 V and the analog supply AVDD.
If the internal reference is required for use external to the
MicroConverter, it should be buffered at the VREF pin and a
100 nF capacitor should be connected from this pin to AGND.
The internal 2.5 V is factory calibrated to an absolute accuracy
of 2.5 V ±50 mV. It should also be noted that the internal VREF
will remain powered down until either of the DACs or the ADC
peripheral blocks are powered on by their respective enable bits.
CalibrationThe ADC block also has four associated calibration SFRs.
These SFR’s drive calibration logic ensuring optimum perfor-
mance from the 12-bit ADC at all times. As part of the power-
on reset configuration, these SFRs are configured automatically
and transparently from factory programmed calibration con-
stants. In many applications use of factory programmed calibra-
tion constants will suffice; however, these calibration SFRs may
be overwritten by user code to further compensate for system-
dependent offset and gain errors.
Calibration OverviewThe ADC block incorporates calibration hardware that ensures
optimum performance from the ADC at all times. The calibra-
tion modes are exercised as part of the ADuC812 internal factory
ADCCON2 – (ADC Control SFR #2)The ADCCON2 register controls ADC channel selection and
conversion modes as detailed below.
SFR Address:D8H
SFR Power On Default Value:00H
Bit Addressable:YES
Table II.ADCCON2 SFR Bit Designations
many applications this autocalibration download function suf-
fices. Alternatively, a device calibration can be easily initiated by
user software to compensate for significant changes in operating
conditions (CLK frequency, analog input range, reference volt-
age and supply voltages).
This in-circuit software calibration feature allows the user to
remove various system and reference related errors (whether it
be internal or external reference) and to make use of the full
dynamic range of the ADC by adjusting the analog input range
of the part for a specific system. Contact Analog Devices, Inc.
for further details on the implementation of the software calibra-
tion routine in your applications.
ADC MODES OF OPERATION
Typical OperationOnce configured via the ADCCON 1-3 SFRs (shown previ-
ously) the ADC will convert the analog input and provide an
ADC 12-bit result word in the ADCDATAH/L SFRs. The top
four bits of the ADCDATAH SFR will be written with the
channel selection bits to identify the channel result. The format
of the ADC 12-bit result word is shown in Figure 5.
Figure 5.ADC Result Format
ADC DMA ModeThe on-chip ADC has been designed to run at a maximum speed
of one sample every 5 µs (i.e., 200 kHz sampling rate). Therefore,
in an interrupt driven routine the user software is required to ser-
vice the interrupt, read the ADC result and store the result for
further post processing, all within 5 µs otherwise the next ADC
sample could be lost. In applications where the ADuC812 can-
not sustain the interrupt rate, an ADC DMA Mode is provided.
The ADC DMA Mode is enabled via the DMA enable bit
(ADCCON2.6), which allows the ADC to sample continuously
as per configuration in ADCCON SFRs. Each sample result is
written into an external Static RAM (mapped in the data memory
space) without any interaction from the ADuC812 core. This
mode ensures the ADuC812 can capture a contiguous sample
stream even at full speed ADC update rates.
Before enabling ADC DMA mode the user must first configure
the external SRAM to which the ADC samples will be written.
This consists of writing the required ADC DMA channels into
the channel ID bits (the top four bits) in the external SRAM. A
typical preconfiguration of external memory is shown in Figure 6.
Once the external data memory has been preconfigured, the
DMA address pointer (DMAP, DMAH and DMAL) SFRs are
written. These SFRs should be written with the DMA start
address in external memory. In Figure 6, for example, the DMA
start address is 000000H. The 3-byte start address should be
written in the following order: DMAL, DMAH and DMAP.
Figure 6.Typical DMA External Memory Preconfiguration
The DMA Enable bit (ADCCON2.6, DMA) can now be set to
initiate the DMA conversion and transfer of the results sequen-
tially into external memory. Remember that the DMA mode
will only progress if the user has preconfigured the ADC
conversion time and trigger modes via the ADCCON1 and 2
SFRs. The end of DMA conversion is signified by the ADC
interrupt bit ADCCON2.7.
At the end of ADC DMA Mode, the external data memory
contains the new ADC conversion results as shown in Figure 7.
It should be noted that the channel selection bits are still present
in the result words to identify the individual conversion results.
Figure 7.Typical External Memory Configuration Post
ADC DMA Operation
Micro Operation during ADC DMA ModeDuring ADC DMA mode the MicroConverter core is free to
continue code execution, including general housekeeping and
communication tasks. However, it should be noted that MCU
core accesses to Ports 0 and 2 (which, of course, are being used
by the DMA controller) are gated “OFF” during ADC DMA
mode of operation. This means that even though the instruction
that accesses the external Ports 0 or 2 will appear to execute, no
data will be seen at these external port pins as a result.
The MicroConverter core is interrupted once the requested
block of DMA data has been captured and written to external
memory allowing the service routine for this interrupt to post-
process the data without any real time, timing constraints.
SFR Interface to the DAC BlockThe ADuC812 incorporates two 12-bit DACs on-chip. DAC
operation is controlled via a single control special function
register and four data special function registers, namely:
DAC0L/DAC1L–Contains the lower 8-bit DAC byte.
ADuC812In normal mode of operation each DAC is updated when the
low DAC nibble (DACxL) SFR is written. Both DACs can be
updated simultaneously using the SYNC bit in the DACCON
SFR.
In 8-bit mode of operation, the 8-bit byte written to the DACxL
registers is automatically routed to the top 8 bits of each 12-bit
DAC. The bit designations of the DACCON SFR are shown
below in Table IV.
SFR Address:FDH
SFR Power On Default Value:04H
Bit Addressable:NO
Table IV.DACCON SFR Bit Designations
NONVOLATILE FLASH MEMORY
Flash Memory OverviewThe ADuC812 incorporates Flash memory technology on-chip
to provide the user with a nonvolatile, in-circuit reprogram-
mable, code and data memory space.
Flash memory is the newest type of nonvolatile memory
technology and is based on a single transistor cell architecture.
This technology is basically an outgrowth of EPROM
technology and was developed through the late 1980s.
Flash memory takes the flexible in-circuit reprogrammable
features of EEPROM and combines them with the space
efficient/density features of EPROM (see Figure 8).
Because Flash technology is based on a single transistor cell
architecture, a Flash memory array, like EPROM can be
implemented to achieve the space efficiencies or memory
densities required by a given design.
Like EEPROM, Flash memory can be programmed in-system at
a byte level, although it must be erased first; the erase being
performed in sector blocks. Thus, Flash memory is often and
more correctly referred to as Flash/EE memory.
Figure 8.Flash Memory Development
Overall, Flash/EE memory represents a step closer towards
the ideal memory device that includes nonvolatility, in-circuit
programmability, high density and low cost. Incorporated in
the ADuC812, Flash/EE memory technology allows the user to
update program code space in-circuit without the need to
replace one-time programmable (OTP) devices at remote
operating nodes.
Flash/EE Memory and the ADuC812The ADuC812 provides two arrays of Flash/EE memory for
user applications.
8K bytes of Flash/EE Program space are provided on-chip to
facilitate code execution without any external discrete ROM
device requirements. The program memory can be programmed
using conventional third party memory programmers. This array
can also be programmed in-circuit, using the serial download
mode provided.
A 640-Byte Flash/EE Data Memory space is also provided on-
chip. This may be used by the user as a general purpose non-
volatile scratchpad area. User access to this area is via a group of
six SFRs. This space can be programmed at a byte level, al-
though it must first be erased in 4-byte sectors.
Using the Flash/EE Program MemoryThis 8K Byte Flash/EE Program Memory array is mapped
into the lower 8K bytes of the 64K bytes program space ad-
dressable by the ADuC812 and will be used to hold user code
Figure 10.Flash/EE Memory Parallel Programming
Table V shows the normal parallel programming modes that can
be configured using Port 3 bits.
Table V.Flash Memory Parallel Programing Modes
Using the Flash/EE Data MemoryThe user Flash/EE data memory array consists of 640 bytes that
are configured into 160 (00H to 9FH), 4-byte pages as shown in
Figure 11.
Figure 11.User Flash/EE Memory Configuration
As with other user peripherals the interface to this memory
space is via a group of registers mapped in the SFR space. A
group of four data registers (EDATA1-4) are used to hold the
4-byte page data just accessed. EADRL is used to hold the 8-bit
address of the page to be accessed. Finally, ECON is an 8-bit
control register that may be written with one of five Flash/EE
memory access commands to enable various read, write, erase
and verify modes.
The program memory array can be programmed in one of two
modes, namely:
Serial Downloading (In-Circuit Programming)As part of its factory boot code, the ADuC812 facilitates serial
code download via the standard UART serial port. Serial down-
load mode is automatically entered on power-up if the external
pin, PSEN, is pulled low through an external resistor as shown
in Figure 9. Once in this mode, the user can download code to
the program memory array while the device is sited in its target
application hardware. A PC serial download executable is pro-
vided as part of the ADuC812 QuickStart development system.
The Serial Download protocol is detailed in a MicroConverter
Applications Note available from ADI.
Figure 9.Flash/EE Memory Serial Download Mode
Programming
Parallel ProgrammingThe parallel programming mode is fully compatible with con-
ventional third party Flash or EEPROM device programmers. A
block diagram of the external pin configuration required to
support parallel programming is shown in Figure 10. In this
mode Ports P0, P1 and P2 operate as the external data and
address bus interface, ALE operates as the Write Enable strobe
and Port P3 is used as a general configuration port that config-
ures the device for various program and erase operations during
parallel programming. The high voltage (12 V) supply required
for Flash programming is generated using on-chip charge pumps
to supply the high voltage program lines.
ADuC812A block diagram of the SFR registered interface to the User
Flash/EE Memory array is shown in Figure 12.
Figure 12.User Flash/EE Memory Control and
Configuration
ECON—Flash/EE Memory Control SFRThis SFR acts as a command interpreter and may be written
with one of five command modes to enable various read, pro-
gram and erase cycles as detailed in Table VI:
Table VI.ECON–Flash/EE Memory Control Register
Command Modes
Flash/EE Memory Write and Erase TimesThe typical program/erase times for the User Flash/EE Memory
are:
Erase Full Array (640 Bytes)–20 ms
Erase Single Page (4 Bytes)–20 ms
Program Page (4 Bytes)–250 µs
Read Page (4 Bytes)–Within Single Instruction Cycle
Using the Flash/EE Memory InterfaceAs with all Flash/EE memory architectures, the array can be pro-
grammed in system at a byte level, although it must be erased
first; the erasure being performed in page blocks (4-byte pages
in this case).
A typical access to the Flash/EE array will involve setting up the
page address to be accessed in the EADRL SFR, configuring the
EDATA1-4 with data to be programmed to the array (the
EDATA SFRs will not be written for read accesses) and finally
writing the ECON command word which initiates one of the
five modes shown in Table VI.
It should be noted that a given mode of operation is initiated as
soon as the command word is written to the ECON SFR. At
this time the core microcontroller operation on the ADuC812
is idled until the requested Program/Read or Erase mode is
completed.
In practice, this means that even though the Flash/EE memory
mode of operation is typically initiated with a 2 machine cycle
MOV instruction (to write to the ECON SFR), the next
instruction will not be executed until the Flash/EE operation
is complete (250 µs or 20 ms later). This means that the core
will not respond to Interrupt requests until the Flash/EE
operation is complete, although the core peripheral functions
like Counter/Timers will continue to count and time as configured
throughout this pseudo-idle period.
ERASE-ALLAlthough the 640-byte User Flash/EE array is shipped from the
factory pre-erased, i.e., Byte locations set to FFH, it is nonethe-
less good programming practice to include an erase-all routine
as part of any configuration/setup code running on the ADuC812.
An “ERASE-ALL” command consists of writing “06H” to the
ECON SFR, which initiates an erase of all 640 byte locations in
the Flash/EE array. This command coded in 8051 assembly
would appear as:
MOV ECON, #06H; Erase all Command
; 20 ms Duration
PROGRAM A BYTEIn general terms, a byte in the Flash/EE array can only be
programmed if it has previously been erased. To be more spe-
cific, a byte can only be programmed if it already holds the value
FFH. Because of the Flash/EE architecture this erasure must
happen at a page level, therefore a minimum of four bytes (1 page)
will be erased when an erase command is initiated.
A more specific example of the Program-Byte process is shown
graphically in Figure 13. In this example the user will write F3H
into the second byte on Page 03H of the User Flash/EE Memory
space.
Figure 13.User Flash/EE Memory Program Byte Example
The new byte is then written to the EDATA2 SFR, followed by
an ERASE cycle that will ensure this page is erased before the
new page data EDATA1-4 is written back into memory.
If the user attempts to initiate a PROGRAM cycle (ECON
set to 02H) without an ERASE cycle (ECON set to 05H),
then only bit locations set to a “1” would be modified, i.e., the
Flash/EE memory byte location must be pre-erased to allow a
valid write access to the array. It should also be noted that the
time durations for an ERASE-ALL command (640 bytes) and
that for an ERASE page command (four bytes) are identical,
i.e., 20 ms.
This example coded in 8051 assembly would appear as :
MOVEADRL, #03H; Set Page Pointer
MOVECON, #01H; Read Page Command
MOVEDATA2, #0F3H; Write New Byte
MOVECON, #02H; Erase Page Command
MOVECON, #05H; Program Page Command
INTERRUPT SYSTEMThe ADuC812 provides nine interrupt sources with two priority
levels. Interrupt priority within a given level is shown in de-
scending order of priority in Figure 14, which gives a general
overview of the interrupt sources and illustrates the request and
control flags. The interrupt vector addresses for corresponding
interrupts are also included in Table VII.
ADuC812
IE2 – (Interrupt Enable 2 SFR )The IE2 register enables two additional interrupt sources.
SFR Address:A9H
SFR Power On Default Value:00H
Bit Addressable:NO
Table IX.Interrupt Enable 2 (IE2) SFR Bit Designations
IP – (Interrupt Priority SFR )The IP register sets one of two main priority levels for the vari-
ous interrupt sources. Set the corresponding bit to “1” to con-
figure interrupt as high priority and to “0” to configure interrupt
as low priority.
SFR Address:B8H
SFR Power On Default Value:00H
Bit Addressable:YES
Table X.Interrupt Priority (IP) SFR Bit Designations
Table VII. Interrupt Vector Addresses
Use of InterruptsTo use any of the interrupts on the ADuC812, the following
three steps must be taken.Locate the interrupt service routine at the corresponding
Vector Address of that interrupt. See Table VII above.Set the EA (enable all) bit in the IE SFR to “1.”Set the corresponding individual interrupt bit in the IE
or IE2 SFR to “1.”
Three SFRs are used to enable and set priority for the various
interrupts. The bit designations of these SFRs are shown in
Tables VIII, IX and X. It should be noted that while IE and IP
SFRs are bit addressable, IE2 is byte addressable only.
IE – (Interrupt Enable SFR)The IE register enables the interrupt system and seven interrupt
sources.
SFR Address:A8H
SFR Power On Default Value:00H
Bit Addressable:YES
Table VIII.Interrupt Enable (IE) SFR Bit Designations
