ADT7518ARQ ,SPI/I2C Compatible/ Temperature Sensor/ Four Channel ADC and Quad Voltage Output DACfeatures a standbymode that is controlled via the serial interface.cont. next pageFUNCTIONAL BLOCK ..
ADT7518ARQZ-REEL ,SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DACSPECIFICATIONS Table 1. Temperature range is as follows: A version: –40°C to +120°C. VDD = 2.7 V t ..
ADT7519ARQ ,SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DACCharacteristics........ 6 Function Description—Voltage Output....... 20 Functional Block Diagram .. ..
ADT7519ARQZ ,SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DACapplications, including personal The ADT7516/ADT7517/ADT7519 provide two serial interface computers ..
ADT7519ARQZ-REEL ,SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DACSpecifications subject to change without notice. No license is granted by implication www.analog.c ..
ADT7519ARQZ-REEL7 ,SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DACCharacteristics ....... 13 SMBus Alert Response 43 Theory of Operation ....... 19 Outline Dimension ..
AM2716B , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2716B-100DC , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2716B-100DI , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2716B-105DC , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2716B-105DI , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
AM2716B-150DC , 2048 X 8 - BIT / 4096 X 8 - BIT EPROM
ADT7518ARQ
SPI/I2C Compatible/ Temperature Sensor/ Four Channel ADC and Quad Voltage Output DAC
REV. PrH 01/’03
SPI/I2C
Compatible, Temperature Sensor, Four
Channel ADC and Quad Voltage Output DAC
PRELIMINARY TECHNICAL DATA
FUNCTIONAL BLOCK DIAGRAM
FEATURES
ADT7516 - Four 12-Bit DACs
ADT7517 - Four 10-Bit DACs
ADT7518 - Four 8-Bit DACs
Buffered Voltage Output
Guaranteed Monotonic By Design Over All Codes
10-Bit Temperature to Digital Converter
10-Bit Four Channel ADC :
DC Input Bandwidth
Input Range: 0 V to 2.25 V
Temperature range:-40oC to +125oC
Temperature Sensor Accuracy of ±0.5oC
Supply Range : + 2.7 V to + 5.5 V
DAC Output Range: 0 - 2VREF
Power-Down Current 1μμμμμA
Internal 2.25 VRef Option
Double-Buffered Input Logic
Buffered Reference Input Option
Power-on Reset to Zero Volts
Simultaneous Update of Outputs (LDAC Function)
On-Chip Rail-to-Rail Output Buffer Amplifier2C
, SPITM, QSPITM, MICROWIRETM and DSP-Compatible 4-
wire Serial Interface
16-Lead QSOP Package
GENERAL DESCRIPTIONThe ADT7516/7517/7518 combines a 10-Bit Tempera-
ture-to-Digital Converter, a 10-Bit Four Channel ADC
and a quad 12/10/8-Bit DAC respectively, in a 16-Lead
QSOP package. This includes a bandgap temperature
sensor and a 10-bit ADC to monitor and digitize the tem-
perature reading to a resolution of 0.25 oC. The
ADT7516/17/18 operates from a single +2.7 V to + 5.5 V
supply. The input voltage range on the ADC channels has
a range of 0V to 2.25V and the input bandwidth is DC.
The reference for the ADC channels is derived internally.
The output voltage of the DAC ranges from 0 V to VDD ,
with an output voltage settling time of typ 7 msec. The
ADT7516/17/18 provides two serial interface options, a
four-wire serial interface which is compatible with SPITM,
QSPITM, MICROWIRETM and DSP interface standards;
and a two-wire SMBus/I2C interface. It features a standby
mode that is controlled via the serial interface.
cont. next page
APPLICATIONS
Portable Battery Powered Instruments
Personal Computers
Smart Battery Chargers
Telecommunications Systems
Electronic Test Equipment
Domestic Appliances
Process ControlI2C is a registered trademark of Philips Corporation
SPI and QSPI are trademarks of Motorola, INC.
MICROWIRE is a trademark of National Semiconductor Corporation.
The ADT7316/7317/7318 is protected by the following U.S. patent
numbers and by other intellectual property rights :
PRELIMINARY TECHNICAL DATA
ADT7516/7517/7518
ADT7516/ADT7517/ADT7518-SPECIFICATIONS1(VDD=2.7 V to 5.5 V, GND=0 V, REFIN=2.25 V, unless otherwise noted)
cont. from P.1
The reference for the four DACs is derived either inter-
nally or from a reference pin. The outputs of all DACs
may be updated simultaneously using the software LDAC
function or external LDAC pin. The ADT7516/7517/
7518 incorporates a power-on-reset circuit, which ensures
that the DAC output powers-up to zero volts and it re-
mains there until a valid write takes place.
The ADT7516/7517/7518’s wide supply voltage range,
low supply current and SPI/I2C-compatible interface,
make it ideal for a variety of applications, including per-
sonal computers, office equipment and domestic appli-
ances.
ADT7516/7517/7518
PRELIMINARY TECHNICAL DATA
PRELIMINARY TECHNICAL DATA
ADT7516/7517/7518POWER REQUIREMENTS
Notes:Temperature ranges are as follows: A Version: -40°C to +125°C.See Terminology.DC specifications tested with the outputs unloaded.Linearity is tested using a reduced code range: ADT7516 (code 115 to 4095); ADT7517 (code 28 to 1023); ADT7518 (code 8 to 255)See Terminology.Round Robin is the continuous sequential measurement of the following channels : VDD, Internal Temperature, External Temperature/
(AIN1, AIN2), AIN3 and AIN4.Guaranteed by Design and Characterization, not production testedIn order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its
maximum voltage (VREF=VDD ) "Offset plus Gain" Error must be positive.The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I2C specification. Switching off the input
filters improves the transfer rate but has a negative affect on the EMC behaviour of the part.Guaranteed by design. Not tested in production. Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
ADT7516/7517/7518
PRELIMINARY TECHNICAL DATA1.6V
IOL200�A
OUTPUT
PIN
Figure 2. Diagram for SPI Bus Timing
DAC AC CHARACTERISTICS1(VDD = +2.7V to +5.5 V; RL=4k7Ω to GND; CL=200pF to GND;
4K7Ω to VDD; All specifications TMIN to TMAX unless otherwise noted.)
NOTESGuaranteed by Design and Characterization, not production testedSee Terminology
Specifications subject to change without notice.
PRELIMINARY TECHNICAL DATA
ADT7516/7517/7518
ABSOLUTE MAXIMUM RATINGS1VDD to GND –0.3 V to +7 V
Analog Input Voltage to GND –0.3 V to VDD + 0.3 V
Digital Input Voltage to GND –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND –0.3 V to VDD + 0.3 V
Reference Input voltage to GND –0.3 V to VDD + 0.3V
Operating Temperature Range –40°C to +125°C
Storage Temperature Range –65°C to +150°C
Junction Temperature +150°C
16-Lead QSOP Package
Power Dissipation2 (Tj max - TA) / θJA
Thermal Impedance3
θJA Junction-to-Ambient 105.44 °C/W
θJC Junction-to-Case38.8 °C/W
IR Reflow Soldering
Peak Temperature +220°C (-0/+5°C)
Time at Peak Temperature 10 to 20 secs
Ramp-up Rate2-3°C/sec
Ramp-down Rate-6°C/sec
Notes:Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above
those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
2Values relate to package being used on a 4-layer board.Junction-to-Case resistance is applicable to components featuring a
preferential flow direction, eg. components mounted on a heat sink.
Junction-to-Ambient resistance is more useful for air-cooled PCB-
mounted components.
ORDERING GUIDE
ModelTemperature RangeDAC ResolutionPackage DescriptionPackage OptionsADT7518ARQ–40°C to +125°C8-Bits16-Lead QSOPRQ-16
ADT7517ARQ-40°C to +125°C10-Bits16-Lead QSOPRQ-16
ADT7516ARQ-40°C to +125°C12-Bits16-Lead QSOPRQ-16
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
PIN CONFIGURATION
QSOP
Table 1. I2C Address Selection
ADD PinI2C AddressLow1001 000
Float1001 010
High1001 011
ADT7516/7517/7518
PRELIMINARY TECHNICAL DATA
ADT7516/7517/7518 PIN FUNCTION DESCRIPTION
PRELIMINARY TECHNICAL DATA
ADT7516/7517/7518
TERMINOLOGY
RELATIVE ACCURACYRelative accuracy or integral nonlinearity (INL) is a mea-
sure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. Typical INL versus Code plots can be seen in
TPCs 1, 2, and 3.
DIFFERENTIAL NONLINEARITYDifferential Nonlinearity (DNL) is the difference be-
tween the measured change and the ideal 1 LSB change
between any two adjacent codes. A specified differential
nonlinearity of ±1 LSB maximum ensures monotonicity.
The DAC and ADC are guaranteed monotonic by design.
Typical DAC DNL versus Code plots can be seen in
TPCs 4, 5, and 6.
OFFSET ERRORThis is a measure of the offset error of the DAC and the
output amplifier. (See Figures 5 and 6.) It can be negative
or positive. It is expressed in mV.
OFFSET ERROR MATCHThis is the difference in Offset Error between any two
channels
GAIN ERRORThis is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic
from the ideal expressed as a percentage of the full-scale
range.
GAIN ERROR MATCHThis is the difference in Gain error between any two chan-
nels.
OFFSET ERROR DRIFTThis is a measure of the change in offset error with
changes in temperature. It is expressed in (ppm of full-
scale range)/°C.
GAIN ERROR DRIFTThis is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-
scale range)/°C.
LONG TERM TEMPERATURE DRIFTThis is a measure of the change in temperature error with
the passage of time. It is expressed in °C/1000hrs. The
concept of long-term stability has been used for many
years to describe by what amount an IC’s parameter would
shift during its lifetime. This is a concept that has been
typically applied to both voltage references and monolithic
temperature sensors. Unfortunately, integrated circuits
cannot be evaluated at room temperature (25°C) for 10
years or so to determine this shift. As a result, manufactur-
ers very typically perform accelerated life-time testing of
integrated circuits by operating ICs at elevated tempera-
is significantly accelerated due to the increase in rates of
reaction within the semiconductor material. As a result of
this operation, the lifetime of an integrated circuit is sig-
nificantly accelerated due to the increase in rates of reac-
tion within the semiconductor material.
DC POWER-SUPPLY REJECTION RATIO (PSRR)This indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the
change in VOUT to a change in VDD for full-scale output of
the DAC. It is measured in dBs. VREF is held at 2 V and
VDD is varied ±10%.
DC CROSSTALKThis is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC
while monitoring another DAC. It is expressed in µV.
REFERENCE FEEDTHROUGHThis is the ratio of the amplitude of the signal at the
DAC output to the reference input when the DAC output
is not being updated (i.e., LDAC is high). It is expressed
in dBs.
CHANNEL-TO-CHANNEL ISOLATIONThis is the ratio of the amplitude of the signal at the out-
put of one DAC to a sine wave on the reference input of
another DAC. It is measured in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGYMajor-code transition glitch energy is the energy of the
impulse injected into the analog output when the code in
the DAC register changes state. It is normally specified as
the area of the glitch in nV secs and is measured when the
digital code is changed by 1 LSB at the major carry transi-
tion (011...11 to 100...00 or 100...00 to
011...11).
DIGITAL FEEDTHROUGHDigital feedthrough is a measure of the impulse injected
into the analog output of a DAC from the digital input
pins of the device but is measured when the DAC is not
being written to the. It is specified in nV secs and is mea-
sured with a full-scale change on the digital input pins,
i.e., from all 0s to all 1s or vice versa.
DIGITAL CROSSTALKThis is the glitch impulse transferred to the output of one
DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of
another DAC. It is measured in stand-alone mode and is
expressed in nV secs.
ANALOG CROSSTALKThis is the glitch impulse transferred to the output of one
DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-
ADT7516/7517/7518
PRELIMINARY TECHNICAL DATAFigure 5. DAC Transfer Function with Negative Offset
DAC-TO-DAC CROSSTALKThis is the glitch impulse transferred to the output of one
DAC due to a digital code change and subsequent out-
put change of another DAC. This includes both digital
and analog crosstalk. It is measured by loading one of the
DACs with a full-scale code change (all 0s to all 1s and
vice versa) with LDAC low and monitoring the output of
another DAC. The energy of the glitch is expressed in nV
secs.
MULTIPLYING BANDWIDTHThe amplifiers within the DAC have a finite bandwidth.
The multiplying bandwidth is a measure of this. A sine
wave on the reference (with full-scale code loaded to the
DAC) appears on the output. The multiplying band-
width is the frequency at which the output amplitude falls
to 3 dB below the input.
TOTAL HARMONIC DISTORTIONThis is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used
as the reference for the DAC, and the THD is a measure of
the harmonics present on the DAC output. It is measured
in dBs.
ROUND ROBINThis term is used to describe the ADT7516/17/18 cycling
through the available measurement channels in sequence,
taking a measurement on each channel.
DAC OUTPUT SETTLING TIMEThis is the time required, following a prescribed data
change, for the output of a DAC to reach and remain
within ±0.5 LSB of the final value. A typical prescribed
change is from 1/4 scale to 3/4 scale.
PRELIMINARY TECHNICAL DATA
ADT7516/7517/7518TPC 1. ADT7518 Typical DAC INL PlotTPC 2. ADT7517 Typical DAC INL PlotTPC 3. ADT7516 Typical DAC INL Plot
TPC 4. ADT7518 Typical DAC DNL PlotTPC 5. ADT7517 Typical DAC DNL PlotTPC 6. ADT7516 Typical DAC DNL Plot
ADT7516/7517/7518
PRELIMINARY TECHNICAL DATATPC 10. DAC Offset Error and Gain
Error vs VDD
TPC 11. DAC VOUT Source and Sink Cur-
rent Capability
TPC 12. Supply Current vs. DAC Code
TPC 13. Supply Current vs. Supply Volt-
age
TPC 14. Power-Down Current vs. Supply
Voltage
TPC 15. DAC Half-Scale Settling (1/4 to
3/4 Scale Code Change)
TPC 16. Exiting Power-Down to MidscaleTPC 17. ADT7516 DAC Major-Code Tran-
TPC 18. DAC Multiplying Bandwidth
PRELIMINARY TECHNICAL DATA
ADT7516/7517/7518TPC 19. DAC Full-Scale Error vs. VREFTPC 20. DAC-to-DAC Crosstalk
TPC 21. ADC DNLTPC 22. ADC INL
ADT7516/7517/7518
PRELIMINARY TECHNICAL DATATPC 25. ADC Offset Error and Gain Error vs TemperatureTPC 26. ADC Offset Error and Gain Error vs VDD
PRELIMINARY TECHNICAL DATA
ADT7516/7517/7518
ADT7516/17/18 OPERATIONDirectly after the power-up calibration routine the
ADT7516/17/18 goes into idle mode. In this mode the
device is not performing any measurements and is fully
powered up. All four DAC outputs are at 0V.
To begin monitoring, write to Control Configuration 1
(address = 18h) register and set bit C0 = 1. The
ADT7516/17/18 goes into it’s power-up default measure-
ment mode, which is Round Robin. The device proceeds
to take measurements on the VDD channel, internal tem-
perature sensor channel, external temperature sensor chan-
nel or AIN1 and AIN2, AIN3 and finally AIN4 . Once it
finishes taking measurements on the AIN4 channel the
device immediately loops back to start taking measure-
ments on the VDD channel and repeats the same cycle as
before. This loop continues until the monitoring is
stopped by resetting bit C0 of Control Configuration 1
register to 0. It is also possible to continue monitoring as
well as switching to Single channel mode by writing to
Control Configuration 2 register (address = 19h) and
setting bit C4 = 1. Further explanation of the Single
channel and Round Robin measurement modes are given
in later sections. All measurement channels have averaging
enabled on them on power-up. Averaging forces the device
to take an average of 16 readings before giving a final
measured result. To disable averaging and consequently
decrease the conversion time by a factor of 16, set C5 = 1
in Control Configuration 2 register.
There are four single ended analog input channels on the
ADT7516/17/18, AIN1 to AIN4. AIN1 and AIN2 are
multiplexed with the external temperature sensors D+ and
D- terminals. Bits C1 and C2 of Control Configuration 1
register (address = 18h) are used to select between AIN1/
2 and external temperature sensor. The input range on the
analog input channels is dependent on whether the ADC
reference used is the internal VREF or VDD. To meet lin-
earity specifications, it is recommended that the maximum
VDD value is 5 V. Bit C4 of Control Configuration 3 reg-
ister is used to select between the internal reference or
VDD as the analog inputs ADC reference.
Controlling the DAC outputs can be done by writing to
the DACs MSB and LSB registers (addresses 10h - 17h).
The power-up default setting is to have a low going pulse
on the LDAC pin (pin 9) controlling the updating of the
DAC outputs from the DAC registers. You can configure
the updating of the DAC outputs to be controlled by
methods other than the LDAC pin by setting C3 = 1 of
the Control Configuration 3 register (address = 1Ah).
The DAC Configuration register (address = 1Bh) and the
LDAC Configuration register (address = 1Ch) can now
be used to control the DAC updating. These two registers
also control the output range of the DACs and selecting
between the internal or external reference. DAC A and
DAC B outputs can be configured to give a voltage output
proportional to the temperature of the internal and exter-
nal temperature sensors respectively.2
locked in, while the SPI protocol on selection is automati-
cally locked in. The interface can only be switched back to
be I2C when the device is powered off and on. When using2C the CS pin should be tied to either VDD or GND.
There are a number of different operating modes on the
ADT7516/17/18 devices and all of them can be controlled
by the configuration registers. These features consist of
the INT/INT pin, enabling and disabling interrupts, po-
larity of the INT/INT pin, enabling and disabling the
averaging on the measurement channels, SMBus timeout
and software reset.
POWER-UP CALIBRATIONIt is recommended that no communication to the part is
initiated until approximately 5ms after VDD has settled to
within 10% of it’s final value. It is generally accepted that
most systems take a maximum of 50ms to power-up.
Power-up time is directly related to the amount of
decoupling on the voltage supply line.
During this 5ms after VDD has settled, the part is perform-
ing a calibration routine and any communication to the
device will interrupt this routine and could cause errone-
ous temperature measurements. If it not possible to have
VDD at it’s nominal value by the time 50ms has elapsed or
that communication to the device has started prior to VDD
settling then it is recommended that a measurement be
taken on the VDD channel before a temperature measure-
ment is taken. The VDD measurement is used to calibrate
out any temperature measurement error due to different
supply voltage values.
FUNCTIONAL DESCRIPTION - VOLTAGE OUTPUT
DACThe ADT7516/7517/7518 has four resistor-string DACs
fabricated on a CMOS process with resolutions of 12, 10
and 8 bits respectively. They contain four output buffer
amplifiers and is written to via I2C serial interface or SPI
serial interface. See Serial Interface Selection section for
more information.
The ADT7516/7517/7518 operates from a single supply
of 2.7 V to 5.5 V and the output buffer amplifiers provide
rail-to-rail output swing with a slew rate of 0.7 V/μs. All
four DACs share a common reference input, namely
VREFIN. The reference input is buffered to draw virtually
no current from the reference source as it offers the source
a high impedance input. The devices have a power-down
mode, in which all DACs may be turned off completely
with a high-impedance output.
Each DAC output will not be updated until it receives the
LDAC command. Therefore while the DAC registers
would have been written to with a new value, this value
will not be represented by a voltage output until the DACs
have received the LDAC command. Reading back from
any DAC register prior to issuing an LDAC command
ADT7516/7517/7518
PRELIMINARY TECHNICAL DATAbe given by either pulling the LDAC pin low (falling
edge loads DACs), setting up Bits D4 and D5 of DAC
Configuration register (address = 1Bh) or using the
LDAC register (address = 1Ch.
When using the LDAC pin to control DAC register load-
ing, the low going pulse width should be 20ns minimum.
The LDAC pin has to go high and low again before the
DAC registers can be reloaded.
Digital-to-Analog SectionThe architecture of one DAC channel consists of a resis-
tor-string DAC followed by an output buffer amplifier.
The voltage at the VREFIN pin or the on-chip reference of
2.25 V provides the reference voltage for the correspond-
ing DAC. Figure 7 shows a block diagram of the DAC
architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by:
VREF * D
VOUT = ----------N
where D=decimal equivalent of the binary code which is
loaded to the DAC register;
0-255 for ADT7518 (8-Bits)
0-1023 for ADT7517 (10-Bits)
0-4095 for ADT7516 (12-Bits)
N = DAC resolution.
Figure 7. Single DAC channel architecture
Resistor StringThe resistor string section is shown in Figure 8. It is sim-
ply a string of resistors, each of value 603Ω approxi-
mately. The digital code loaded to the DAC register
determines at what node on the string the voltage is tapped
off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because it is a string of resistors, it
is guaranteed monotonic.
Figure 8. Resistor String
DAC Reference InputsThere is an input reference pin for the DACs. This refer-
ence input is buffered.
Figure 9. DAC Reference Buffer Circuit
The advantage with the buffered input is the high imped-
ance it presents to the voltage source driving it. The user
can have an external reference voltage as low as 1 V and as
high as VDD. The restriction of 1 V is due to the footroom
of the reference buffer.
The LDAC Configuration register controls the option to
select between internal and external voltage references.
The default setting is for external reference selected.
Output AmplifierThe output buffer amplifier is capable of generating out-
put voltages to within 1mV of either rail. Its actual range
depends on the value of VREF, GAIN and offset error.
If a gain of 1 is selected (Bits 0-3 of DAC Configuration
register = 0) the output range is 0.001 V to VREF.
If a gain of 2 is selected (Bits 0-3 of DAC Configuration
register = 1) the output range is 0.001 V to 2VREF. How-
PRELIMINARY TECHNICAL DATA
ADT7516/7517/7518Figure 10. Signal Conditioning for External Diode Temperature Sensor
The output amplifier is capable of driving a load of 4k7Ω
to GND or VDD, in parallel with 200pF to GND or VDD.
See Figure 4. The source and sink capabilities of the out-
put amplifier can be seen in the plot in TPC 11.
The slew rate is 0.7V/μs with a half-scale settling time to
+/-0.5 LSB (at 8 bits) of 6μs.
THERMAL VOLTAGE OUTPUTThe ADT7516/17/18 has the capability of outputting a
voltage that is proportional to temperature. DAC A output
can be configured to represent the temperature of the in-
ternal sensor while DAC B output can be configured to
represent the external temperature sensor. Bits C5 and C6
of Control Configuration 3 register select the temperature
proportional output voltage. Each time a temperature
measurement is taken the DAC output is updated. The
output resolution for the ADT7518 is 8 bits with 1°C
change corresponding to one LSB change. The output
resolution for the ADT7516 and ADT7517 is capable of
10 bits with 0.25°C change corresponding to one LSB
change. The default output resolution for the ADT7516
and ADT7517 is 8 bits. To increase this to 10 bits, set
C1 = 1 of Control Configuration 3 register. The default
output range is 0V-VREF and this can be increased to 0V-
2VREF. Increasing the output voltage span to 2VREF can be
done by setting D0 = 1 for DAC A (Internal Temperature
Sensor) and D1 = 1 for DAC B (External Temperature
Sensor) in DAC Configuration register (address 1Bh).
The output voltage is capable of tracking a max tempera-
ture range of -128°C to +127°C but the default setting is -
40°C to +127°C. If the output voltage range is 0V-VREF
(VREF = 2.25 V) then this corresponds to 0V representing
-40°C and 1.48V representing +127°C. This of course
will give an upper deadband between 1.48V and VREF.
output voltage span of VREF and 2VREF respectively. Sim-
ply write in the temperature value, in 2’s complement
format, that you want 0V to start at. For example, if you
are using the DAC A output and you want 0V to start at -
40°C then program D8h into the Internal Analog Tem-
perature Offset register (address 21h). This is an 8-bit
register and thus only has a temperature offset resolution
of 1°C for all device models. Use the following formulas
to determine the value to program into the offset registers.
Negative temperatures : -
Offset Register Code(d)* = (0V Temp) + 128
*D7 of Offset Register Code is set to 1 for negative temperatures.
Example :
Offset Register Code(d) = (-40) + 128
= 88d = 58h
Since a negative temperature has been inputted into the
equation, DB7 (MSB) of the Offset Register code is set to
a 1. Therefore 58h becomes D8h.
58h + DB7(1) ⇒ D8h
Positive temperatures : -
Offset Register Code(d) = 0V Temp
Example :
Offset Register Code (d) = 10d = 0Ah
Table 2. Thermal Voltage Output (0V-VREF)
O/P VoltageDefault °CMax °CSample °C-40-1280
0.5V+17-71+56
ADT7516/7517/7518
PRELIMINARY TECHNICAL DATA1.47V+127+39UDB*
1.5VUDB*+42UDB*UDB*+99UDB*
2.25VUDB*+127UDB*
* Upper deadband has been reached. DAC output is not capable of
increasing. Reference Figure 6.
Table 3. Thermal Voltage Output, (0V-2VREF)
O/P VoltageDefault °CMax °CSample °C-40-1280
0.25V-26-11414
0.5V+12-100+28
0.75V+3-8543+17-71+57
1.12V+23-65+63
1.47V+43-45+83
1.5V+45-43+85+73-15+113
2.25V+880+127
2.5V+102+14UDB*
2.75V+116+28UDB*UDB*+42UDB*
3.25VUDB*+56UDB*
3.5VUDB*+70UDB*
4.5VUDB*+127UDB*
* Upper deadband has been reached. DAC output is not capable of
increasing. Reference Figure 6.
The following equation is used to work out the various
temperatures for the corresponding 8-bit DAC output :-
8-Bit Temp = (DAC O/P ÷ 1 LSB) + ( 0V Temp)
For example, if the output is 1.5V, VREF = 2.25 V, 8-bit
DAC has an LSB size = 2.25V/256 = 8.79x10-3, and 0V
Temp is at -128°C then the resultant temperature works
out to be :-
(1.5 ÷ 8.79x10-3) + (-128) = +43°C
The following equation is used to work out the various
temperatures for the corresponding 10-bit DAC output :-
10-Bit Temp = ((DAC O/P ÷ 1 LSB)x0.25) + ( 0V Temp)
For example, if the output is 0.4991V, VREF = 2.25 V, 10-
bit DAC has an LSB size = 2.25V/1024 = 2.197x10-3,
and 0V Temp is at -40°C then the resultant temperature
works out to be :-
((0.4991 ÷2.197x10-3)x0.25) + (-40) = +16.75°C
Figure 12 shows a graph of DAC output vs temperature
for a VREF = 2.25 V.
Figure 11. Top Level Structure of Internal Temperature Sensor
PRELIMINARY TECHNICAL DATA
ADT7516/7517/7518Figure 12. DAC Output vs Temperature, VREF = 2.25 V
FUNCTIONAL DESCRIPTION - ANALOG INPUTS
SINGLE-ENDED INPUTSThe ADT7516/17/18 offers four single-ended analog in-
put channels. The analog input range is between 0 V to
2.25 V or 0 V to VDD. To maintain the linearity specifica-
tion it is recommendated that the maximum VDD value be
set at 5 V. Selection between the two input ranges is done
by Bit C4 of Control Congifuration 3 Register (Address =
1Ah). Setting this bit to 0 sets up the analog input ADC
reference to be sourced from the internal voltage reference
of 2.25 V. Setting the bit to 1 sets up the ADC reference
to be sourced from VDD.
The ADC resolution is 10 bits and is mostly suitable for
DC input signals. Bits C1:2 of Control Configuration 1
register (Address = 18h) are used to set up pins 7 and 8 as
AIN1 and AIN2. Figure 13 shows the overall view of the
four channel analog input path.
Figure 13. Quad Analog Input Path
CONVERTER OPERATIONThe analog input channels use a successive approximation
ADC based around a resistor-string DAC. Figures 14 and
15 show simplified schematics of the ADC. Figure 14
shows the ADC during acquisition phase. SW2 is closed
and SW1 is in position A. The comparator is held in a
balanced condition and the sampling capacitor acquires
the signal on AIN.
Figure 14. ADC Acquisition Phase
When the ADC eventually goes into conversion phase, see
Figure 15, SW2 opens and SW1 moves to position B
causing the comparator to become unbalanced. The con-
trol logic and the DAC are used to add and subtract fixed
amounts of charge from the sampling capacitor to bring
the comparator back into a balanced condition. When the
comparator is rebalanced the conversion is complete. The
control logic generates the ADC output code. Figure 16
shows the ADC transfer function for the analog inputs.
ADT7516/7517/7518
PRELIMINARY TECHNICAL DATAFigure 15. ADC Conversion Phase
ADC TRANSFER FUNCTIONThe output coding of the ADT7516/17/18 analog inputs
is straight binary. The designed code transitions occur
midway between successive integer LSB values (i.e. 1/
2LSB, 3/2LSB, etc.). The LSB is VDD/1024 or Int VREF/
1024, Int VREF = 2.25 V. The ideal transfer characteristic
is shown in figure 16 below.
0V1/2LSB+VREF-1LSB
ANALOGINPUT
1LSB=IntVREF/1024
1LSB=VDD/1024
Figure 16. Single-Ended Transfer Function
To work out the voltage on any analog input channel, the
following method can be used:
1 LSB = Reference (v) / 1024
Convert value read back from AIN Value register into
decimal.
AIN Voltage = AIN Value (d) x LSB size
d = decimal
Example:
Internal Reference used. Therefore Vref = 2.25 V.
AIN Value = 512d
1 LSB size = 2.25 V / 1024 = 2.197x10-3
AIN Voltage = 512 x 2.197x10-3
= 1.125 V
must be taken that the analog input signal never drops
below the GND rail by more than 200mV. If this happens
then the diode will become forward biased and start con-
ducting current into the substrate. The 4pF capacitor is
the typical pin capacitance and the resistor is a lumped
component made up of the on-resistance of the multi-
plexer switch.
Figure 17. Equivalent Analog Input ESD Circuit
AIN INTERRUPTSThe measured results from the AIN inputs are compared
with the AIN VHIGH (greater than comparsion) and VLOW (
less than and equal to comparsion) limits. An interrupt
occurs if the AIN inputs exceed or equal the limit regis-
ters. These voltage limits are stored in on-chip registers.
Please note that the limit registers are 8 bits long while
the AIN conversion result is 10 bits long. If the voltage
limits are not masked out then any out of limit compari-
sons generate flags that are stored in Interrupt Status 1
Register (address = 00h) and one or more out-of limit
results will cause the INT/INT output to pull either high
or low depending on the output polarity setting. It is good
design practice to mask out interrupts for channels that are
of no concern to the application.
Figure 18 showes the interrupt structure for the
ADT7516/17/18. It gives a block diagram representation
of how the various measurement channels affect the INT/INT pin.
FUNCTIONAL DESCRIPTION - MEASUREMENT
TEMPERATURE SENSORThe ADT7516/7517/7518 contains an A-D converter with
special input signal conditioning to enable operation with
external and on-chip diode temperature sensors. When the
ADT7516/7517/7518 is operating in single channel mode,
the A to D converter continually processes the measure-
ment taken on one channel only. This channel is
preselected by bits C0:C2 in Control Configuration 2
Register (address 19h). When in Round Robin mode the
analog input multiplexer sequentially selects the VDD in-
put channel, the on-chip temperature sensor to measure its
internal temperature, either the external temperature sen-
sor or AIN1 and AIN2, AIN3 and then AIN4. These sig-
nals are digitized by the ADC and the results stored in the
various Value Registers.
The measured results from the temperature sensors are
compared with the Internal and External, THIGH, TLOW
PRELIMINARY TECHNICAL DATA
ADT7516/7517/7518limit results will cause the INT/INT output to pull either
high or low depending on the output polarity setting.
Theoretically, the temperature sensor and ADC can mea-
sure temperatures from -128oC to +127oC with a resolu-
tion of 0.25oC. However, temperatures outside TA are
outside the guaranteed operating temperature range of the
device. Temperature measurement from -128oC to
+127oC is possible using an external sensor.
Temperature measurement is initiated by three methods.
The first method is applicable when the part is in single
channel measurement mode. The temperature is measured
16 times and internally averaged to reduce noise. The
total time to measure a temperature channel is typically
25.92ms (1.62ms x 16) for the internal temperature sensor
and 16.8ms (1.05ms x 16) for the external temperature
sensor. The new temperature value is loaded into the
Temperature Value Register and ready for reading by the2C or SPI interface. The user has the option of disabling
the averaging by setting a bit (Bit 5) in the Control Con-
figuration Register 2 (address 19h). The ADT7516/7517/
7518 defaults on power-up with the averaging enabled.
The second method is applicable when the part is in
Round Robin measurement mode. The part measures both
the internal and external temperature sensors as it cycles
through all possible measurement channels. The two tem-
perature channels are measured each time the part runs a
round robin sequence. In round robin mode the part is
continuously measuring all channels.
Temperature measurement is also initiated after every read
will start again immediately after the serial communica-
tion has finished. The temperature measurement proceeds
normally as described above.
VDD MONITORINGThe ADT7516/17/18 also has the capability of monitoring
it’s own power supply. The part measures the voltage on
it’s VDD pin to a resolution of 10 bits. The resultant value
is stored in two 8-bit registers, the two LSBs stored in
register address 03h and the eight MSBs are stored in
register address 06h. This allows the user to have the op-
tion of just doing a one byte read if 10-bit resolution is not
important. The measured result is compared with VHIGH
and VLOW limits. If the VDD interrupt is not masked out
then any out-of-limit comparison generates a flag in Inter-
rupt Status 2 Register and one or more out-of-limit results
will cause the INT/INT output to pull either high or low
depending on the output polarity setting.
Measuring the voltage on the VDD pin is regarded as
monitoring a channel along with the Internal, External
and AIN channels. You can select the VDD channel for
single channel measurement by setting Bit C4 = 1 and
setting Bit C0 to Bit C2 to all 0’s in Control Configura-
tion 2 register.
When measuring the VDD value the reference for the ADC
is sourced from the Internal Reference. Table 4 shows the
data format. As the max VCC voltage measurable is 7 V,
internal scaling is performed on the VCC voltage to match
the 2.25V internal reference value. Below is an example of
how the transfer function works.
Figure 18. ADT7516/17/18 Interrupt Structure
