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ADT7470ARQZ-REEL |ADT7470ARQZREELADIN/a84avaiTemperature Sensor Hub and Fan Controller
ADT7470ARQZ-REEL7 |ADT7470ARQZREEL7ADN/a64avaiTemperature Sensor Hub and Fan Controller
ADT7470ARQZADIN/a196avaiTemperature Sensor Hub and Fan Controller
ADT7470ARQZ-REEL |ADT7470ARQZREELADN/a2580avaiTemperature Sensor Hub and Fan Controller


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ADT7470ARQZ-ADT7470ARQZ-REEL-ADT7470ARQZ-REEL7
Temperature Sensor Hub and Fan Controller
Temperature Sensor Hub and Fan ControllerRev. PrA
FEATURES
Monitors up to 10 remote temperature sensors
Monitors and controls speed of up to 4 fans independently
PWM outputs drive each fan under software control
FULL_SPEED input allows fans to be blasted 100% by
external hardware
SMBALERT interrupt signals failures to system controller
Tristate ADDR pin allows up to 3 devices on a single bus
Temperature decoder interprets TMP05/TMP06 temperature
sensors and communicates values over I2C bus
Limit comparison of all monitored values
Supports fast I2C standard (400 kHz max)
Meets SMBus 2.0 electrical specifications
(fully SMBus 1.1 compliant)
Footprint compatible with ADT7460
APPLICATIONS
Servers
Networking and telecommunications equipment
Desktops
GENERAL DESCRIPTION

The ADT7470 controller is a multichannel temperature sensor
and PWM fan controller and fan speed monitor for noise-
sensitive systems requiring active system cooling. It is designed
to interface directly to an I2C bus and control/monitor the fans
using a service processor. The aim is to quickly develop systems
that are modular and can easily be expanded depending on the
system’s cooling requirements. The device can monitor up to ten
temperature sensors. It can also monitor and control the speed
of four fans so that they operate at the lowest possible speed for
minimum acoustic noise. A FULL_SPEED input is provided to
allow the fans to be “blasted” to 100% via external hardware
control, under extreme thermal conditions or on system startup.
An SMBALERT interrupt communicates error conditions such
as fan underspeed, fan failure to the system service processor.
Individual error conditions can then be read from status registers
over the I2C bus. In the event of a fan failure condition, any or
all PWM outputs can be programmed to automatically adjust to
100% to provide failsafe cooling.
FUNCTIONAL BLOCK DIAGRAM
PWM1
PWM2
PWM3
PWM4
TACH1
TACH2
TACH3
TACH4
TMP_START
TMP_IN
ADDRSDASCL

Figure 1.
Protected by Patent Numbers US6,188,189, US6,169,442, US6,097,239, US5,982,221, US5,867,012. Other patents pending.
TABLE OF CONTENTS
Specifications.....................................................................................3
Absolute Maximum Ratings............................................................5
Thermal Characteristics..............................................................5
ESD Caution..................................................................................5
Pin Configuration and Function Descriptions.............................6
Functional Description....................................................................7
General Description.....................................................................7
Fan Speed Measurement..............................................................7
ADT7470 Address Selection.......................................................7
Internal Registers of the ADT7470............................................7
SMBus/I2C Communications Interface.....................................7
ADT7470 Write Operations......................................................10
ADT7470 Read Operations.......................................................11
SMBus Timeout..........................................................................11
Temperature Measurement Using TMP05/TMP06...................12
Measuring Temperature............................................................12
TMP05/TMP06 Decoder...........................................................12
Interrupt Functionality and Status Registers..............................13
Limit Values.................................................................................13
8-Bit Limits..................................................................................13
16-Bit Limits...............................................................................13
Out-of-Limit Comparisons.......................................................14
Monitoring Cycle Time.............................................................15
Status Registers...........................................................................15
SMBALERT Interrupt Behavior...............................................16
Handling SMBALERT Interrupts.............................................16
Masking Interrupt Sources........................................................17
Enabling the SMBALERT Interrupt Output...........................17
Fan Drive Using PWM Control....................................................18
Fan Speed Measurement................................................................19
Tach Inputs..................................................................................19
Fan Speed Measurement...........................................................19
Manual Fan Speed Control...........................................................22
PWM Logic State........................................................................22
Manual Fan Speed Control.......................................................22
Automatic Fan Speed Control..................................................22
ADT7470 Registers........................................................................23
Outline Dimensions.......................................................................38
Ordering Guide..........................................................................38
REVISION HISTORY

Revision 0: Initial Version
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.
Table 1.
Note the following about the specifications for the ADT7470: All voltages are measured with respect to GND, unless otherwise specified. Typical values are at TA = 25°C and represent most likely parametric norm. Logic inputs accept input high voltages up to 5 V even when device is operating at supply voltages below 5 V. VDD should never be floated in presence of SCL/SDA activity. Charge injection can be sufficient to induce approximately 0.6 V on
VDD. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
SCL
SDA
tSU;DATtSU;STOtF
Figure 2. Diagram for Serial Bus Timing
ABSOLUTE MAXIMUM RATINGS
Table 2.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS

16-Lead QSOP Package:
θJA = 105°C/Watt, θJC = 39°C/Watt
ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SDA
PWM1
SMBALERT
FULL_SPEED/TMP_START
TMP_IN
ADDR
PWM4
TACH4
SCL
GND
VCC
TACH3
PWM2
TACH1
TACH2
PWM3

04684-0-003
Figure 3. RQ-16
Table 3. Pin Function Descriptions

FUNCTIONAL DESCRIPTION
GENERAL DESCRIPTION

The ADT7470 is a multichannel PWM fan controller and
monitor for any system requiring monitoring and cooling. The
device communicates with the system via a serial system
management bus. The device has a single address line for
address selection (Pin 11), a serial data line for reading and
writing addresses and data (Pin 16), and an input line for the
serial clock (Pin 1). All control and programming functions of
the ADT7470 are performed over the serial bus that supports
both SMBus and fast I2C specifications. In addition, an
SMBALERT interrupt output is provided to indicate out-of-
limit conditions.
FAN SPEED MEASUREMENT

When the ADT7470 monitoring sequence is started, it cycles
through each fan tach input to measure fan speed. Measured
values from these inputs are stored in value registers. These can
be read out over the serial bus, or can be compared with
programmed limits stored in the limit registers. The results of
out of limit comparisons are stored in the status registers, which
can be read over the serial bus to flag out of limit conditions. If
fan speeds drop below preset levels or a fan stalls, an interrupt is
generated and the fans can automatically blast to 100%.
Likewise, the ADT7470 has the ability to flag fan overspeed
conditions using fan tach max registers.
ADT7470 ADDRESS SELECTION

Pin 11 is the address selection pin, ADDR. If Pin 11 is pulled
low on power-up, the ADT7470 defaults to Slave Address 0x58
(left-justified) or 0x2C (right-justified). If Pin 11 is floating on
power-up, then the ADT7470 defaults to SMBus slave Address
0x5A (left-justified) or 0x2D (right-justified). By pulling the pin
high on power-up, the SMBus slave address is 0x5C (left-
justified) or 0x2E (right-justified).
INTERNAL REGISTERS OF THE ADT7470

A brief description of the ADT7470’s principal internal registers
is given in the following sections. More detailed information on
the function of each register is found in the register map in
Table 21.
Configuration Registers

These registers provide control and configuration of the
ADT7470, including alternate pinout functionality such as a fan
blast input (FULL_SPEED) or daisy-chained TMP05 measure-
ment (start) output.
Address Pointer Register

This register contains the address that selects one of the other
internal registers. When writing to the ADT7470, the first byte
Status Registers

These registers provide status of each limit comparison and are
used to signal out-of-limit conditions on the fan speed channels,
or temperature channels if monitored using the PWM_IN
feature. If Pin 14 (SMBALERT) is used in the system, then this
pin asserts low whenever a status bit gets set, signaling an out-
of-limit condition.
Interrupt Mask Registers

Allows each interrupt status event to be individually masked
from driving the SMBALERT output as required. This is useful
where fan tach inputs is unused and left floating, or if temperature
inputs from TMP05s are ignored from an interrupt perspective.
Masking interrupt status bits prevents the SMBALERT output
from being driven although the status bits still reflect out-of-
limit conditions. This can prevent a service processor from being
continually tied up in an interrupt service routine, should a
value remain outside limits for a relatively long duration.
Value and Limit Registers

The results of fan speed measurements are stored in these
registers, along with their limit values. The limit values store the
slowest speed that the fans are expected to run at, or the limit
value can determine what a fan failure is expected to be, in
terms of running speed in case the fan doesn’t completely stall.
If TMP05s and TMP06s are daisy-chained in through the
PWM_IN pin, then the measured temperatures are stored in
temperature value registers.
TMIN Registers

Programs the starting temperature for each fan under automatic
fan speed control. The ADT7470 has limited automatic fan
speed control capability where only one mode of operation is
supported. If TMP05s are daisy-chained in, the fastest speed
calculated, determined by the measured temperature, TMIN and a
fixed slope of 20°C can drive each fan. Fan on/off hysteresis is
set at 4°C so that the fans turn off 4°C below the temperature at
which they turn. This prevents fan chatter in the system.
SMBus/I2C COMMUNICATIONS INTERFACE
Serial Bus Interface

Control of the ADT7470 is carried out using the serial system
management bus (SMBus). This interface is fully compatible
with SMBus 2.0 electrical specifications and meets 400 pF bus
capacitance requirements. The device also supports fast I2C
(400 kHz max). The ADT7470 is connected to the bus as a slave
device, under the control of a master controller or service
processor.
The ADT7470 has a 7-bit serial bus address. When the device is
powered up with Pin 11 (ADDR) high, the ADT7470 has an
SMBus address of 0101111 or 0x5E (left-justified). Because the
floating or tied low for other addressing options as shown in
Table 4.
Table 4. ADT7470 Address Select Mode

VCC
10kΩ
TYP.

04684-0-004
Figure 4. SMBus Address = 0x5E or 0x2F (Pin 11 = 1)
04684-0-005
Figure 5. SMBus Address = 0x58 or 0x2C (Pin 11 = 0)
04684-0-006
Figure 6. SMBus Address = 0x5C or 0x2E (Pin 11 = Floating)
The device address is sampled and latched on the first valid
SMBus transaction, so any additional attempted addressing
changes have no immediate effect. The facility to make
hardwired changes to the SMBus slave address allows the user
to avoid conflicts with other devices sharing the same serial bus,
for example, if more than one ADT7470 is used in a system.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, defined as a high to low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
start condition, and shift in the next 8 bits, consisting of a
7-bit address (MSB first) and a R/W bit, which determines
the direction of the data transfer, i.e., whether data is
written to or read from the slave device.
The peripheral whose address corresponds to the transmit-
ted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit. All other devices on the bus now remain
idle while the selected device waits for data to be read from
or written to it. If the R/W bit is a 0, then the master writes
to the slave device. If the R/W bit is a 1, the master reads
from the slave device.
2. Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, as a low to high transition when
the clock is high may be interpreted as a stop signal. The
number of data bytes that can be transmitted over the
serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
3. When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device overrides
the acknowledge bit by pulling the data line high during
the low period before the 9th clock pulse. This is known as
No Acknowledge. The master then takes the data line low
during the low period before the 10th clock pulse, then
high during the 10th clock pulse to assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and subsequently cannot be changed without
starting a new operation.
SCL
SCL (CONTINUED)
SDA (CONTINUED)
START BY
MASTER
ACK. BY
ADT7470
ACK. BY
ADT7470
ACK. BY
ADT7470
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA
BYTE
Figure 7. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
SCL
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
STOP BY
MASTER
ACK. BY
ADT7470
ACK. BY
ADT74701

04684-0-008
Figure 8. Writing to the Address Pointer Register Only
SCL
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
DATA BYTE FROM
ADT7470
STOP BY
MASTER
ACK. BY
ADT7470
NO ACK.
BY MASTER1
Figure 9. Reading Data from a Previously Selected Register
In the case of the ADT7470, write operations contain either one
or two bytes, and read operations contain one byte, and perform
the following functions.
To write data to one of the device data registers or read data
from it, the address pointer register must be set so that the
correct data register is addressed, then data can be written into
that register or read from it. The first byte of a write operation
always contains an address that is stored in the address pointer
register. If data is to be written to the device, then the write
operation contains a second data byte that is written to the
This is illustrated in Figure 7. The device address is sent over the
bus followed by R/W set to 0. This is followed by two data bytes.
The first data byte is the address of the internal data register to
be written to, which is stored in the address pointer register. The
second data byte is the data to be written to the internal data
register.
When reading data from a register there are two possibilities: If the ADT7470 address pointer register value is unknown
or not the desired value, it is first necessary to set it to the
as before, but only the data byte containing the register
address is sent, as data is not to be written to the register.
This is shown in Figure 8.
A read operation is then performed consisting of the serial
bus address, R/W bit set to 1, followed by the data byte read
from the data register. This is shown in Figure 9. If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register, so Figure 8 can be omitted.
Notes:
Although it is possible to read a data byte from a data
register without first writing to the address pointer register
if the address pointer register is already at the correct value,
it is not possible to write data to a register without writing
to the address pointer register, because the first data byte of
a write is always written to the address pointer register. In Figure 7 to Figure 9, the serial bus address is shown as
the default value 01011(A1)(A0), where A1 and A0 are set
by the address select mode function previously defined. In addition to supporting the send byte and receive byte
protocols, the ADT7470 also supports the read byte
protocol. See System Management Bus specifications
Rev. 2.0 for more information. If it is required to perform several read or write operations
in succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
ADT7470 WRITE OPERATIONS

The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADT7470 are discussed in the following sections. The following
abbreviations are used in the diagrams:
S—Start
P—Stop
R—Read
W—Write
A—Acknowledge
A—No Acknowledge
The ADT7470 uses the following SMBus write protocols:
Send Byte

In this operation, the master device sends a single command
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7470, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This is illustrated in Figure 10. 3456
04684-0-010
Figure 10. Setting a Register Address for Subsequent Read
If it is required to read data from the register immediately after
setting up the address, the master can assert a repeat start
condition immediately after the final ACK and carry out a
single-byte read without asserting an intermediate stop
condition.
Write Byte

In this operation, the master device sends a command byte and
one data byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
This is illustrated in Figure 11. 345678
04684-0-011
ADT7470 READ OPERATIONS
The ADT7470 uses the following SMBus read protocols:
Receive Byte

This is useful when repeatedly reading a single register. The
register address needs to have been set up previously. In this
operation, the master device receives a single byte from a slave
device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
In the ADT7470, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation.
04684-0-012
Figure 12. Single-Byte Write from a Register
Alert Response Address

Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as an interrupt output or
can be used as an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
occurs:
1. SMBALERT is pulled low.
2. Master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
3. The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known, and it can
be interrogated in the usual way.
4. If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority, in
accordance with normal SMBus arbitration.
5. Once the ADT7470 has responded to the alert response
address, the master must read the status registers, and the
SMBALERT is cleared only if the error condition has gone
away.
SMBus TIMEOUT

The ADT7470 includes an SMBus timeout feature. If there is no
SMBus activity for 35 ms, the ADT7470 assumes that the bus is
locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it can
be disabled.
Table 5. Configuration Register 1—Register 0x40

TEMPERATURE MEASUREMENT USING TMP05/TMP06
MEASURING TEMPERATURE

For more information, refer to the TMP05/TMP06 data sheets.
TMP05 generates a PWM output proportional to temperature,
which can be easily interfaced to most micros or CPUs.
The following table lists the temperature reading registers on
the ADT7470.
Table 6. Temperature Reading Registers

8-bit temperature values are reported in the preceding registers
only if the PWM_IN function is used and if TMP05s/TMP06s
are daisy-chained according to their respective data sheets and
connected as shown in Figure 13. Note that this device does
NOT have any temperature measurement capability when used
as a standalone device, without TMP05s/TMP06s connected.
TMP05/TMP06 DECODER

The ADT7470 includes a PWM processing engine to decode the
daisy-chained PWM output from multiple TMP05s/TMP06s
and passes each decoded temperature value to temperature
value registers. This allows the ADT7470 to do high/low limit
comparisons of temperature and to automatically control fan
speed based on measured temperature. The PWM processing
engine contains all necessary logic to initiate start conversions
on the first daisy-chained TMP05/TMP06 and synchronize with
each temperature value as it is fed back to the device through
the daisy chain. The start function is multiplexed on to the same
pin that can be used to blast the fans to full speed. The start
conversion for TMP05/TMP06 temperature measurement is
fully transparent to the user and doesn’t require any software
intervention to function.
SCL
GND
VCC
PWM2
PWM3

Figure 13. Interfacing the ADT7470 to Multiple Daisy-Chained TMP05/TMP06 Temperature Sensors
INTERRUPT FUNCTIONALITY AND STATUS REGISTERS
LIMIT VALUES

Associated with each measurement channel on the ADT7470
are high and low limits. These can form the basis of system
status monitoring: a status bit can be set for any out-of-limit
condition and be detected by polling the device. Alternatively,
SMBALERT interrupts can be generated to automatically flag a
service processor or microcontroller of out-of-limit conditions
as they occur.
8-BIT LIMITS

The following table lists the 8-bit limits on the ADT7470.
Table 7. Temperature Limit Registers (8-Bit Limits)

16-BIT LIMITS

The fan tach measurements are 16-bit results. The fan tach
limits are also 16-bits; consisting of 2 bytes; a high byte and low
byte. On the ADT7470 it is possible to set both high and low
speed fan limits for overspeed and underspeed or stall conditions.
Be aware that since fan tach period is actually being measured,
exceeding the limit by 1 indicates a slow or stalled fan. Likewise,
exceeding the high speed limit by 1 generates an overspeed
condition.
Table 8. Fan Underspeed Limit Registers

Table 9. Fan Overspeed Limit Registers

OUT-OF-LIMIT COMPARISONS
Once all limits have been programmed, the ADT7470 can be
enabled monitoring. The ADT7470 measures all parameters in
round-robin format and set the appropriate status bit for out-of-
limit conditions. Comparisons are done differently depending
on whether the measured value is being compared to a high or
low limit.
High Limit: > Comparison Performed
Low Limit: ≤ Comparison Performed
NO INT
LOW LIMIT
TEMP >LOW LIMIT

Figure 14. Temperature > Low Limit—No INT
INT
LOW LIMIT
TEMP =
LOW LIMIT

04684-0-015
Figure 15. Temperature = Low Limit—INT Occurs
NO INT
HIGH LIMIT
TEMP =
HIGH LIMIT

04684-0-016
Figure 16. Temperature = High Limit—No INT
HIGH LIMIT
INT
TEMP >
HIGH LIMIT

04684-0-017
Figure 17. Temperature > High Limit—INT Occurs
MONITORING CYCLE TIME
The monitoring cycle begins when a one is written to the start
bit (Bit 0) of Configuration Register 1 (Register 0x40). Each fan
tach input is monitored in turn, and as each measurement is
completed, the result is automatically stored in the appropriate
value register. Multiple temperature channels can also be moni-
tored by clocking in temperatures by using the PWM_IN pin.
The temperature measurement function is addressed in hardware
and requires no software intervention. The monitoring cycle
continues unless disabled by writing a 0 to Bit 0 of Configuration
Register 1.
The rate of temperature measurement updates depends on the
nominal conversion rate of the TMP05/TMP06 temperature
sensor (approximately 120 ms) and on the number of TMP05s
daisy-chained together. The total monitoring cycle time is the
temperature conversion time multiplied by the number of
temperature channels being monitored.
Fan tach measurements are taken in parallel and are not
synchronized with the temperature measurements in any way.
STATUS REGISTERS

The results of limit comparisons are stored in Status Registers 1
and 2. The status register bit for each channel reflects the status
of the last measurement and limit comparison on that channel.
If a measurement is within limits, the corresponding status
register bit is cleared to 0. If the measurement is out-of-limits,
the corresponding status register bit is set to 1.
The state of the various measurement channels may be polled
by reading the status registers over the serial bus. Bit 7 (OOL) of
Status Register 1 (Register 0x41) when 1 means that an out-of-
limit event has been flagged in Status Register 2. This means
that you need to read Status Register 2 only when the OOL bit is
set. Alternatively, Pin 11 operates as an SMBALERT output and
can be connected back to the system service processor. This
automatically notifies the system supervisor of an out-of-limit
condition. Reading the status registers clears the appropriate
status bit as long as the error condition that caused the interrupt
has cleared. Status register bits are “sticky.” Whenever a status bit
is set, indicating an out-of-limit condition, it remains set even if
the event that caused it has gone away (until read). The only way
to clear the status bit is to read the status register when the event
has gone away. Interrupt status mask registers (Registers 0x72
and 0x73) allow individual interrupt sources to be masked from
causing an SMBALERT. However, if one of these masked
interrupt sources goes out-of-limit, its associated status bit is
still set in the interrupt status registers. This allows the device to
be periodically polled to determine if an error condition has
subsided, without unnecessarily tying up precious system
resources handling interrupt service routines. The issue is that
the device could potentially interrupt the system every monitor-
ing cycle (< 1 sec) as long as a measurement parameter remains
out-of-limit. Masking eliminates unwanted system interrupts.
MONITORED THROUGH STATUS REG 2
IS OUT-OF-LIMIT
04684-0-018
Figure 18. Interrupt Status Register 1
Table 10. Interrupt Status Register 1 (Register 0x41)

TIMER IS OUT-OF-LIMIT
04684-0-019
Figure 19. Interrupt Status Register 2
Table 11. Interrupt Status Register 2 (Register 0x42)

SMBALERT INTERRUPT BEHAVIOR

The ADT7470 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the SMBALERT output and status bits
behave when writing interrupt handler software.
"STICKY"STATUSBIT
HIGH LIMIT
TEMPERATURE
SMBALERT

04684-0-020
Figure 20. SMBALERT and Status Bit Behavior
Figure 20 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides AND the status register are read. The status bits are
referred to as sticky since they remain set until read by software.
This ensures that an out-of-limit event cannot be missed if
software is polling the device periodically. Note that the
SMBALERT output remains low for the entire duration that a
reading is out-of-limit and until the status register has been
read. This has implications on how software handles the
interrupt.
HANDLING SMBALERT INTERRUPTS

To prevent the system from being tied up servicing interrupts, it
is recommend to handle the SMBALERT interrupt as follows:
"STICKY"
STATUS
BIT
HIGH LIMIT
TEMPERATURE
SMBALERT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
(SMBALERT REARMED)

04684-0-021
Figure 21. How Masking the Interrupt Source Affects SMBALERT Output
1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt source.
4. Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Registers 0x72 and 0x73).
5. Take the appropriate action for a given interrupt source.
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
MASKING INTERRUPT SOURCES
Interrupt Mask Registers 1 and 2 are located at Addresses 0x72
and 0x73. These allow individual interrupt sources to be masked
out to prevent unwanted SMBALERT interrupts. Note that
masking an interrupt source only prevents the SMBALERT
output from being asserted; the appropriate status bit is still set
as usual. This is useful if the system polls the monitoring
devices periodically to determine whether or not out-of-limit
conditions have subsided, without tying up time-critical system
resources.
ENABLING THE SMBALERT INTERRUPT OUTPUT

The SMBALERT interrupt output is a dedicated function that is
provided on Pin 14 to signal out-of-limit conditions to a host or
system processor. Because this is a dedicated function, it is
important that limit registers get programmed before monitoring
gets enabled, to prevent spurious interrupts occurring on the
SMBALERT pin. Although the SMBALERT output cannot be
specifically disabled, interrupt sources can be masked to prevent
SMBALERT assertions. Monitoring is enabled when Bit 0
(STRT) of Configuration Register 1 (Register 0x40) is set to 1.
Table 12. Interrupt Mask Register 1 (Register 0x72)

Table 13. Interrupt Mask Register 2 (Register 0x73)

FAN DRIVE USING PWM CONTROL
The ADT7470 uses pulse width modulation (PWM) to control
fan speed. This relies on varying the duty cycle (or on/off ratio)
of a square wave applied to the fan, to vary the fan speed. Two
main control schemes are used: low frequency and high
frequency PWM. For low frequency, low-side drive, the external
circuitry required to drive a fan using PWM control is extremely
simple. A single NMOS FET is the only drive device required.
The specifications of the MOSFET depends on the maximum
current required by the fan being driven. Typical notebook fans
draw a nominal 170 mA, therefore SOT devices can be used
where board space is a concern. In desktops, fans can typically
draw 250 mA to 300 mA each. If the user need to drive several
fans in parallel from a single PWM output, or drive larger server
fans, the MOSFET needs to handle the higher current require-
ments. The only other stipulation is that the MOSFET should
have a gate voltage drive, VGS < 3.3 V for direct interfacing to
the PWM_OUT pin of the TSM devices. VGS of the chosen
MOSFET can be greater than 3.3 V as long as the pull-up on its
gate is tied to 5 V. The MOSFET should also have a low on-
resistance to ensure that there is not significant voltage drop
across the FET. This would reduce the voltage applied across the
fan and therefore the maximum operating speed of the fan.
Figure 22 shows how a 3-wire fan can be driven using low
frequency PWM control where the control method is low-side,
low frequency switching.
12V
12V
1N4148

Figure 22. Driving a 3-Wire Fan Using an N-Channel MOSFET
Figure 22 shows the ideal interface when interfacing a tach
signal from a 12 V fan (or greater voltage) to a 5 V (or less) logic
device. In all cases, the tach signal from the fan must be kept
below 5 V maximum to prevent damage to the ADT7470. The
three resistors in Figure 22 ensure that the tach voltage is kept
within safe levels for typical desktop and notebook systems.
Figure 23 shows a fan drive circuit using an NPN transistor such
as a general-purpose MMBT2222. While these devices are
inexpensive, they tend to have much lower current handling
meets the fan’s current requirements. This is the only major
difference between a MOSFET and NPN transistor fan driver
circuit.
When using transistors, ensure that the base resistor is chosen
such that the transistor is fully saturated when the fan is
powered on. Otherwise, there are power inefficiencies in the
implementation.
12V
MMBT2222
12V
1N4148

04684-0-023
Figure 23. Driving a 3-Wire Fan Using an NPN Transistor
12V
1N4148

Figure 24. Driving a 4-Wire Fan
High Frequency vs. Low Frequency

One of the important features of fan controllers is the PWM
drive frequency. Today, most fans are driven asynchronously at
low frequency (30 Hz to 100 Hz).Going forward, the devices
drive fans at >20 kHz. These controllers are meant to drive
4-wire fans with PWM control built-in internal to the fan. Note
that the ADT7470 supports high frequency PWM (>20 kHz) as
well as 1.4 kHz and other low frequency PWM. This allows the
user to drive 3-wire or 4-wire fans.
FAN SPEED MEASUREMENT
TACH INPUTS

Pins 6, 7, 4, and 9 are open-drain tach inputs intended for fan
speed measurement.
Signal conditioning in the ADT7470 accommodates the slow
rise and fall times typical of fan tachometer outputs. The
maximum input signal range is 0 V to 5 V, even where VCC is less
than 5 V. In the event that these inputs are supplied from fan
outputs that exceed 0 V to 5 V, either resistive attenuation of the
fan signal or diode clamping must be included to keep inputs
within an acceptable range. Figure 25 to Figure 28 show circuits
for most common fan tach outputs.
If the fan tach output has a resistive pull-up to VCC then it can
be connected directly to the fan input, as shown in Figure 25.
12V
VCC

Figure 25. Fan with Tach Pull-Up to +VCC
If the fan output has a resistive pull-up to 12 V (or other voltage
greater than 5 V) then the fan output can be clamped with a
Zener diode, as shown in Figure 26. The Zener diode voltage
should be chosen so that it is greater than VIH of the tach input
but less than 5 V, allowing for the voltage tolerance of the Zener.
A value of between 3 V and 5 V is suitable.
12V
*CHOOSE ZD1 VOLTAGE APPROX. 0.8
× VCC
VCC

04684-0-026
Figure 26. Fan with Tach.
Pull-up to voltage >5 V, for example., 12 V clamped with Zener diode.
If the fan output has a resistive pull-up to 12 V (or other voltage
greater than 5 V), then the fan output can be clamped with a
Zener diode, as shown in Figure 26. The Zener diode voltage
should be chosen so that it is greater than VIH of the tach input
but less than 5 V, allowing for the voltage tolerance of the Zener.
A value of between 3 V and 5 V is suitable. If the fan has a
strong pull-up (less than 1 kΩ) to 12 V, or a totem-pole output,
then a series resistor can be added to limit the Zener current, as
shown in Figure 27. Alternatively, a resistive attenuator may be
R1 and R2 should be chosen such that
2 V < VPULL-UP × R2/(RPULL-UP + R1 + R2) < 5 V
The fan inputs have an input resistance of nominally 160 kΩ to
ground, so this should be taken into account when calculating
resistor values.
With a pull-up voltage of 12 V and pull-up resistor less than
1 kΩ, suitable values for R1 and R2 would be 100 kΩ and 47 kΩ.
This gives a high input voltage of 3.83 V.
12V
*CHOOSE ZD1 VOLTAGE APPROX. 0.8
× VCC
VCC

04684-0-027
Figure 27. Fan with Strong Tach.
Pull-up to >VCC or totem-pole output, clamped with zener and resistor.
12V
VCC
*SEE TEXT

04684-0-028
Figure 28. Fan with Strong Tach.
Pull-up to > VCC or totem-pole output, attenuated with R1/R2.
FAN SPEED MEASUREMENT

The fan counter does not count the fan tach output pulses
directly, because the fan speed may be less than 1000 RPM and
it would take several seconds to accumulate a reasonably large
and accurate count. Instead, the period of the fan revolution is
measured by gating an on-chip 90 kHz oscillator into the input
of a 16-bit counter for N periods of the fan tach output, as shown
in Figure 29, so the accumulated count is actually proportional
to the fan tachometer period and inversely proportional to the
fan speed.
N, the number of pulses counted is determined by the settings
of Register 0x43 (fan pulses per revolution register). This register
contains two bits for each fan, allowing 1, 2 (default), 3, or 4 tach
pulses to be counted.
CLOCK
PWM
TACH

Figure 29. Fan Speed Measurement
Fan Speed Measurement Registers

The fan tachometer readings are 16-bit values consisting of a
2-byte read from the ADT7470.
Table 14. Fan Speed Measurement Registers

Reading Fan Speed from the ADT7470

If fan speeds are being measured, this involves a 2-register read
for each measurement. The low byte should be read first. This
causes the high byte to be frozen until both high and low byte
registers have been read from. This prevents erroneous tach
readings.
The fan tachometer reading registers report back the number of
11.11 ms period clocks (90 kHz oscillator) gated to the fan
speed counter, from the rising edge of the first fan tach pulse to
the rising edge of the third fan tach pulse (assuming 2 pulses
per revolution is being counted). Since the device is essentially
measuring the fan tach period, the higher the count value, the
slower the fan is actually running. A 16-bit fan tachometer
reading of 0xFFFF indicates either that the fan has stalled or is
running very slowly (<100 RPM).
High Limit: Comparison Performed

Because the actual fan tach period is being measured, exceeding
a fan tach limit by 1 sets the appropriate status bit and can be
used to generate an SMBALERT.
Fan Tach Limit Registers

The fan tach limit registers are 16-bit values consisting of two
bytes. Minimum limits determine fan underspeed limits while
maximum limits determine fan overspeed settings.
Table 15. Fan Tach Limit Registers

Fan Speed Measurement Rate

The fan tach readings are normally updated once every second.
Calculating Fan Speed

Assuming a fan with 2 pulses/revolution (and 2 pulses/rev being
measured) fan speed is calculated by
Fan Speed (RPM) = (90,000 × 60)/ Fan Tach Reading
where Fan Tach Reading is the 16-bit fan tachometer reading.
For example:

Tach 1 High Byte (Reg 0x2B) = 0x17
Tach 1 Low Byte (Reg 0x2A) = 0xFF
What is Fan 1 speed in RPM
Fan 1 tach reading = 0x17FF = 6143 decimal.
RPM = (f × 60)/Fan 1 tach reading
RPM = (90000 × 60)/6143
Fan Speed = 879 RPM
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