ADS62P25IRGCT ,Dual 12-bit 125MSPS ADC with selectable DDR LVDS or CMOS outputs 64-VQFN -40 to 85FEATURES• High Definition Video• Medical Imaging• Maximum Sample Rate: 125 MSPS• Radar Systems• 12- ..
ADS62P28IRGCR ,Dual Channel 12 Bit, 210 MSPS ADC with DDR LVDS & Parallel CMOS outputs 64-VQFN -40 to 85MAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)VALUE UNITSupply v ..
ADS62P28IRGCT ,Dual Channel 12 Bit, 210 MSPS ADC with DDR LVDS & Parallel CMOS outputs 64-VQFN -40 to 85FEATURES • Supports Input Clock Amplitude Down to 400mV Differential• Maximum Sample Rate: 250 MSPS ..
ADS62P29IRGCR ,Dual Channel 12 Bit, 250 MSPS ADC with DDR LVDS & Parallel CMOS outputs 64-VQFN -40 to 85MAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)VALUE UNITSupply v ..
ADS62P29IRGCT ,Dual Channel 12 Bit, 250 MSPS ADC with DDR LVDS & Parallel CMOS outputs 64-VQFN -40 to 85FEATURES • Supports Input Clock Amplitude Down to 400mV Differential• Maximum Sample Rate: 250 MSPS ..
ADS62P42IRGCR ,Dual 14-bit 65MSPS ADC with selectable DDR LVDS or CMOS outputs 64-VQFN -40 to 85FEATURES• Medical Imaging• Radar Systems• Maximum Sample Rate: 125 MSPS• Test and Measurement Instr ..
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ADS62P25IRGCT
Dual 12-bit 125MSPS ADC with selectable DDR LVDS or CMOS outputs
ADS62P24, ADS62P25
ADS62P22, ADS62P23
www.ti.com SLAS576C –OCTOBER 2007–REVISED OCTOBER 2011
DUAL CHANNEL, 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
Checkfor Samples: ADS62P24, ADS62P25, ADS62P22, ADS62P23
1FEATURES •
High Definition Video Medical Imaging•
Maximum Sample Rate: 125 MSPS Radar Systems•
12-Bit Resolution with No Missing Codes 95 dB Crosstalk DESCRIPTION•
Parallel CMOS and DDR LVDS Output Options ADS62P2Xisa dual channel 12-bit A/D converter•
3.5 dB Coarse Gain and Programmable Fine family with maximum sample rates upto 125 MSPS.
Gain upto6 dB for SNR/SFDR Trade-Off It combines high performance and low power
consumptionina compact 64 QFN package. Using•
Digital Processing Block with: internal sample and hold and low jitter clock–
Offset Correction buffer, the ADC supports high SNR and high SFDRat–
Fine Gain Correction,in Stepsof 0.05 dB high input frequencies.It has coarse and fine gain
options that can be used to improve SFDR–
Decimation by 2/4/8performanceat lower full-scale input ranges.–
Built-in and Custom Programmable 24-Tap
Low-/High-/Band-Pass Filters ADS62P2X includesa digital processing block that
consistsof several useful and commonly used digital•
Supports Sine, LVPECL, LVDS, and LVCMOS functions such as ADC offset correction, fine gain
Clocks and Amplitude Downto 400 mVPP correction (in stepsof 0.05 dB), decimation by 2,4,8•
Clock Duty Cycle Stabilizer and in-built and custom programmable filters. By
Internal Reference; Supports External default, the digital processing blockis bypassed, and
Reference also its functions are disabled.
64-QFN Package (9mm×
9mm) Two output interface options exist– parallel CMOS
and DDR LVDS (Double Data Rate). ADS62P2X•
Pin Compatible 14-Bit Family (ADS62P4X)includes internal references while traditional
reference pins and associated decoupling capacitors
APPLICATIONS have been eliminated. Nevertheless, the device can•
Wireless Communications Infrastructure alsobe driven with an external reference. The device specified over the industrial temperature range•
Software Defined Radio(–40°Cto 85°C).•
Power Amplifier Linearization 802.16d/e
