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ADS61B23IRHBTTI/BB N/a5avai12-bit, 80MSPS ADC with buffered differential inputs 32-VQFN -40 to 85


ADS61B23IRHBT ,12-bit, 80MSPS ADC with buffered differential inputs 32-VQFN -40 to 85features exist toease data capture—controls for output clock position• Clock Duty Cycle Stabilizera ..
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ADS61B23IRHBT
12-bit, 80MSPS ADC with buffered differential inputs 32-VQFN -40 to 85
1FEATURES
DESCRIPTION
APPLICATIONS
ADS61B23

SLAS582–FEBRUARY 2008www.ti.com
12-BIT, 80-MSPS ADC WITH BUFFERED ANALOG INPUTS
Maximum Sample Rate:80 MSPS 12-bit Resolution with No Missing Codes ADS61B23isa 12-bit A/D converter (ADC) witha
maximum sampling frequency of 80 MSPS. It• Buffered Analog Inputs with combines high performance and low power– Very Low Input Capacitance(<2 pF) consumptionina compact 32-QFN package. The High DC Resistance(5 kΩ) analog inputs use buffersto isolate the switching
transientsof the internal sample& hold from the• 82 dBc SFDR and70 dBFS SNR external driving circuit. The buffered inputs present(-1 dBFSor 1.8 Vpp input) very low input capacitance(< 2pF)& wide bandwidth.• 85 dBc SFDR (-6 dBFSor1 Vpp input) This makesit easy to drive them at high input• 3.5 dB Coarse Gain and upto6 dB frequencies, comparedto an ADC without the input
buffers.Programmable Fine Gain for SNR and SFDR
Trade-Off
ADS61B23 has coarse and fine gain options that are• Parallel CMOS and Double Data Rate (DDR) used to improve SFDR performance at lower
LVDS Output Options
full-scale analog input ranges. Supports Sine, LVCMOS, LVPECL, LVDS Clock The digital data outputs are parallel CMOSor DDRInputs and Clock Amplitude Downto 400 mVPP LVDS (Double Data Rate). Several features existto
ease data capture—controls for output clock position• Clock Duty Cycle Stabilizer
and output buffer drive strength, plus LVDS current• Internal Reference with Support for External and internal termination programmability.Reference
The output interface type, gain, and other functions• External Decoupling Eliminated for References are programmed usinga 3-wire serial interface.• Programmable Output Clock Position and Alternatively, someof these functions are configuredDrive Strengthto Ease Data Capture using dedicated parallel pins so the device startsin 3.3V Analog and 1.8Vto 3.3V Digital Supply the desired state after power-up. 32-pin QFN Package(5 mm×5 mm) ADS61B23 includes internal references, while
eliminating the traditional reference pins and• Pin Compatible 12-Bit Family (ADS612X)
associated external decoupling. External reference• Temperature range –40°Cto 85°C modeis also supported. Wireless Communications Infrastructure Software Defined Radio Power Amplifier Linearization 802.16d/e Test and Measurement Instrumentation High Definition Video Medical Imaging Radar Systems
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