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ADP3402ARUADN/a50avaiGSM Power Management System
ADP3402ARUADIN/a344avaiGSM Power Management System


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ADP3402ARU
GSM Power Management System
REV.0
FEATURES
Handles all GSM Baseband Power Management
Functions
Four LDOs Optimized for Specific GSM Subsystems
Charges Back-Up Capacitor for Real-Time Clock
Charge Pump and Logic Level Translators for 3 V and 5 V
GSM SIM Modules
Thermally Enhanced 6.1 mm 28-Lead TSSOP Package
APPLICATIONS
GSM/DCS/PCS Handsets
TeleMatic Systems
ICO/Iridium Terminals
GSM Power Management System
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION

The ADP3402 is a multifunction power management system IC
optimized for GSM cell phones. The wide input voltage range of
3.0 V to 7.0 V makes the ADP3402 ideal for both single cell
Li-Ion and three cell NiMH designs. The current consumption of
the ADP3402 has been optimized for maximum battery life,
featuring a ground current of only 230 mA when the phone is in
standby (digital LDO, analog LDO, and SIM card supply active).
An undervoltage lockout (UVLO) prevents the startup when
there is not enough energy in the battery. All four integrated
LDOs are optimized to power one of the critical sub-blocks of the
phone. Their novel anyCAP™ architecture requires only very
small output capacitors for stability, and the LDOs are insensitive
to the capacitors’ equivalent series resistance (ESR). This makes
them stable with any capacitor, including ceramic (MLCC) types
for space-restricted applications.
A step-up converter is implemented to supply both the SIM
module and the level translation circuitry to adapt logic signals
for 3 V and 5 V SIM modules. Sophisticated controls are avail-
able for power-up during battery charging, keypad interface and
charging of an auxiliary back-up capacitor for the real-time clock.
These allow an easy interface between ADP3402, GSM proces-
sor, charger, and keypad. The 28-lead TSSOP package has been
thermally enhanced to maximize power dissipation capability.
Furthermore, a reset circuit and a thermal shutdown function
have been implemented to support reliable system design.
anyCAP is a trademark of Analog Devices, Inc.
ADP3402–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS1

OPERATING GROUND CURRENT
UVLO CHARACTERISTICS
INPUT CHARACTERISTICS
CHRON CHARACTERISTICS
SHUTDOWN
DIGITAL LDO (VCC)
(–20°C £ TA £ +85°C, VBAT = 3 V to 7 V, CVBAT = CSIMBAT = CVSIM = 10 mF,
CVCC = CVCCA = 2.2 mF, CVRTC = 0.1 mF, CVTCXO = 0.22 mF, CVCAP = 0.1 mF, minimum loads
applied on all outputs, unless otherwise noted)
ADP3402
ADP3402–SPECIFICATIONS
NOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125ºC. Operation beyond 125ºC
could cause permanent damage to the device.Required for stability.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin with Respect to Any
GND Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +10 V
Voltage on Any Pin May Not Exceed VBAT,
with the Following Exceptions: VRTC,
VSIM, CAP+, PWRONIN, I/O, CLK, RST
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Operating Temperature Range . . . . . . . . . . .–20°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . .125°CJA, Thermal Impedance (TSSOP-28) . .2-Layer Board 90°C/WJA, Thermal Impedance (TSSOP-28) . .4-Layer Board 60°C/W
Lead Temperature Range (Soldering, 60 sec) . . . . . . . .300°C
*This is a stress rating only, operation beyond these limits can cause the device to
be permanently damaged.
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3402 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
ORDERING GUIDE
ADP3402
Table I. LDO Control Logic

X = Don't care
Bold denotes the active control signal.
VCC
2.45V
DGND
VRTC
2.45V
REFOUT
AGND
VCCA
2.765V
VTCXO
2.765V
VBAT
PWRONKEY
ROWX
PWRONIN
RESCAPRESET
CHRON
ANALOGON
SIMBAT
CAP+
CAP2
SIMPROG
SIMON
SIMGND
RESETIN
CLKIN
DATAIO
Table II. VSIM Control Logic

X = Don't care
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