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ADMC326YR
28-Lead ROM-Based DSP Motor Controller
REV.A
28-Lead ROM-Based
DSP Motor Controller
FUNCTIONAL BLOCK DIAGRAM
TARGET APPLICATIONS
Washing Machines, Refrigerator Compressors, Fans,
Pumps, Industrial Variable Speed Drives, Automotive
MOTOR TYPES
AC Induction Motors
Permanent Magnet Synchronous Motors (PMSM)
Brushless DC Motors (BDCM)
FEATURES
20 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512 3 24-Bit Program Memory RAM
4K 3 24-Bit Program Memory ROM
512 3 16-Bit Data Memory RAM
Three-Phase 16-Bit PWM Generator
16-Bit Center-Based PWM Generator
Programmable Dead Time and Narrow Pulse Deletion
Edge Resolution to 50 ns
150 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for Each PWM Output
High Frequency Chopping Mode for Transformer
Coupled Gate Drives
External PWMTRIP Pin
Integrated ADC Subsystem
Six Analog Inputs
Acquisition Synchronized to PWM Switching Frequency
Internal Voltage Reference
9-Pin Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 8-Bit Auxiliary PWM Timers
Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Double Buffered Synchronous Serial Port
Hardware Support for UART Emulation
Integrated Power-On Reset Function
28-Lead SOIC or PDIP Package Options
ADMC326–SPECIFICATIONS
(VDD = +5 V 6 5%, GND = 0 V, TA = –408C to +1058C for ADMC326Y, TA = –408C to
+1258C for ADMC326T, CLKIN = 10 MHz, unless otherwise noted)
ANALOG-TO-DIGITAL CONVERTERLinearity Error
Zero Offset
Channel-to-Channel Comparator Match
Comparator Delay
ADC Hi-Level Input Current
NOTESResolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.2.44 kHz sample frequency, V1, V2, VAUX0, VAUX1, VAUX2.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICSIDD
NOTESOutput pins PIO0–PIO8, AH, AL, BH, BL, CH, CL.XTAL Pin.Internal Pull-Up, RESET.Internal Pull-Down, PWMTRIP, PIO0–PIO8.Three-stateable pins DT1, RFS1, TFS1, SCLK1.Outputs not Switching.
Specifications subject to change without notice.
CURRENT SOURCE1NOTESFor ADC Calibration.0.3 V to 3.5 V ICONST Voltage.
Specifications subject to change without notice.
ADMC326
VOLTAGE REFERENCENOTESThis specification for voltage level (VREF) is for SOIC package only, at specified temperature range.
Specifications subject to change without notice.
POWER-ON RESETNOTES216 CLKOUT Cycles.
Specifications subject to change without notice.
ADMC326
TIMING PARAMETERSall relevant timing parameters to obtain specification value.
Example: tCKH = 0.5 tCK – 10 ns = 0.5 (50 ns) – 10 ns = 15 ns.
Timing Requirements:
tCKIN
NOTESApplies after power-up sequence is complete.
Specifications subject to change without notice.
Figure 1.Clock Signals
tSCDE
Specifications subject to change without notice.
CLKOUT
SCLK
RFSIN
TFSIN
RFSOUT
TFSOUT
TFS
(ALTERNATE
FRAME MODE)
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 [MFD = 0])
tTDEFigure 2.Serial Port Timing
ADMC326
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC326 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage (VDD) . . . . . . . . . . . . . . . . . .–0.3 V to +7.0 V
Input Voltage . . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient)
ADMC326Y . . . . . . . . . . . . . . . . . . . . . .–40°C to +105°C
ADMC326T . . . . . . . . . . . . . . . . . . . . . .–40°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . .280°C
*Stresses greater than those listed may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ORDERING GUIDENOTES
xxx = customer identification code.
yy = ROM identification code.
To place an order for a custom ROM-coded ADMC326 processor, please request a copy of the ADMC ROM ordering package, available from your Analog Devices
Sales representative.
Analog Devices assesses a charge for each ROM mask generated in addition to a minimum order quantity. Please consult your sales representative for details.
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONV1
PWMTRIP
VDD
XTAL
CLKIN
PIO6/CLKOUT
PIO5/RFS1
PIO4/DR1A
PIO3/SCLK1
PIO0/TFS1
PIO1/DT1
PIO2/DR1B
VAUX0
VAUX1
VAUX2
ICONST
GND
RESET
PIO7/AUX1
PIO8/AUX0
GENERAL DESCRIPTIONThe ADMC326 is a low cost, single-chip DSP-based controller,
suitable for permanent magnet synchronous motors, AC induction
motors and brushless dc motors. The ADMC326 integrates a
20 MIPS, fixed-point DSP core with a complete set of motor
control and system peripherals that permits fast, efficient
development of motor controllers.
The DSP core of the ADMC326 is the ADSP-2171, which is
completely code compatible with the ADSP-21xx DSP family
and combines three computational units, data address generators
and a program sequencer. The computational units comprise an
ALU, a multiplier/accumulator (MAC) and a barrel shifter. The
ADSP-2171 adds new instructions for bit manipulation, multipli-
cation (· squared), biased rounding and global interrupt masking.
The system peripherals are the power-on reset circuit (POR),
the watchdog timer and a synchronous serial port. The serial
port is configurable and double buffered, with hardware support
for UART and SCI port emulation.
The ADMC326 provides 512 · 24-bit program memory RAM,
4K · 24-bit program memory ROM and 512 · 16-bit data
memory RAM. The program memory ROM contains the user-
specified program code and is defined using a single metal layer
mask. The program and data memory RAM can be used for
dynamic data storage.
The motor control peripherals of the ADMC326 comprise a
12-bit analog data acquisition system with six analog input
channels and an internal voltage reference. In addition, a three-
phase, 16-bit, center-based PWM generation unit can be used to
produce high accuracy PWM signals with minimal processor
overhead. The ADMC326 also contains two auxiliary PWM
outputs, and nine lines of digital I/O.
Because the ADMC326 has a limited number of pins, a number
of functions such as the auxiliary PWM and the serial commu-
nication port are multiplexed with the nine programmable input/
output (PIO) pins. The pin functions can be independently
selected to allow maximum flexibility for different applications.
R BUSFigure 3.DSP Core Block Diagram
ADMC326
DSP CORE ARCHITECTURE OVERVIEWFigure 3 is an overall block diagram of the DSP core of the
ADMC326, which is based on the fixed-point ADSP-2171. The
flexible architecture and comprehensive instruction set of the
ADSP-2171 allow the processor to perform multiple operations
in parallel. In one processor cycle (50 ns with a 10 MHz CLKIN)
the DSP core can:Generate the next program address.Fetch the next instruction.Perform one or two data moves.Update one or two data address pointers.Perform a computational operation.
This all takes place while the processor continues to:Receive and transmit through the serial port.Decrement the interval timer.Generate three-phase PWM waveforms for a power inverter.Generate two signals using the 8-bit auxiliary PWM timers.Acquire four analog signals.Decrement the watchdog timer.
The processor contains three independent computational units:
the arithmetic and logic unit (ALU), the multiplier/accumulator
(MAC) and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision com-
putations. The ALU performs a standard set of arithmetic and
logic operations as well as providing support for division primi-
tives. The MAC performs single-cycle multiply, multiply/add,
and multiply/subtract operations with 40 bits of accumulation.
The shifter performs logical and arithmetic shifts, normalization,
denormalization and derive-exponent operations. The shifter
can be used to efficiently implement numeric format control, in-
cluding floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps and
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMC326 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and pro-
gram memory. Each DAG maintains and updates four address
pointers (I registers). Whenever the pointer is used to access
data (indirect addressing), it is post-modified by the value in
one of four modify (M registers). A length value may be associ-
ated with each pointer (L registers) to implement automatic
modulo addressing for circular buffers. The circular buffering
feature is also used by the serial ports for automatic data trans-
fers to and from on-chip memory. DAG1 generates only data
memory address and provides an optional bit-reversal capability.
DAG2 may generate either program or data memory addresses
but has no bit-reversal capability.
Efficient data transfer is achieved with the use of five internal
buses:Data memory data (DMD) bus.Result (R) bus.
Program memory can store both instructions and data, permit-
ting the ADMC326 to fetch two operands in a single cycle—
one from program memory and one from data memory. The
ADMC326 can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
The ADMC326 writes data from its 16-bit registers to the 24-bit
program memory using the PX register to provide the lower
eight bits. When it reads data (not instructions) from 24-bit pro-
gram memory to a 16-bit data register, the lower eight bits are
placed in the PX register.
The ADMC326 can respond to a number of distinct DSP core
and peripheral interrupts. The DSP interrupts comprise a serial
port receive interrupt, a serial port transmit interrupt, a timer
interrupt, and two software interrupts. Additionally, the motor
control peripherals include two PWM interrupts and a PIO
interrupt.
The serial port (SPORT1) provides a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed and unframed data transmit and receive
modes of operation. SPORT1 can generate an internal program-
mable serial clock or accept an external serial clock.
A programmable interval counter is also included in the DSP
core and can be used to generate periodic interrupts. A 16-bit
count register (TCOUNT) is decremented every n processor
cycles, where n–1 is a scaling value stored in the 8-bit TSCALE
register. When the value of the counter reaches zero, an interrupt
is generated, and the count register is reloaded from a 16-bit
period register (TPERIOD).
The ADMC326 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Each instruction is executed in a single 50 ns pro-
cessor cycle (for a 10 MHz CLKIN). The ADMC326 assembly
language uses an algebraic syntax for ease of coding and read-
ability. A comprehensive set of development tools supports
program development. For further information on the DSP
core, refer to the ADSP-2100 Family User’s Manual, Third Edition,
with particular reference to the ADSP-2171.
Serial PortThe ADMC326 incorporates a complete synchronous serial
port (SPORT1) for serial communication and multiprocessor
communication. The following is a brief list of capabilities of the
ADMC326 SPORT1. Refer to the ADSP-2100 Family User’s
Manual, Third Edition, for further details.SPORT1 is bidirectional and has a separate, double-buffered
transmit and receive section.SPORT1 can use an external serial clock or generate its own
serial clock internally.SPORT1 has independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame synchronization signals are active high or inverted,
with either of two pulsewidths and timings.
SPORT1 receive and transmit sections can generate uniqueinterrupts on completing a data word transfer.SPORT1 can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1), and the Flag In and Flag Out signals.
The internally generated serial clock may still be used in this
configuration.SPORT1 has two data receive pins (DR1A and DR1B), which
are internally multiplexed onto the one DR1 port of the
SPORT1. The particular data receive pin selected is deter-
mined by a bit in the MODECTRL register.
PIN FUNCTION DESCRIPTIONThe ADMC326 is available in a 28-lead SOIC package and a
28-lead PDIP package. Table I describes the pins.
Table I.Pin ListCLKOUT
CLKIN, XTAL
PIO0–PIO8
AUX0–AUX1
AH–CL
PWMTRIP
V1, V2, V3
VAUX0–VAUX2
ICONST
VDD
NOTEMultiplexed pins, selectable individually through the PIOSELECT and
PIODATA1 registers.
INTERRUPT OVERVIEWThe ADMC326 can respond to 16 different interrupt sources
with minimal overhead, five of which are internal DSP core
interrupts and 11 are from the motor control peripherals. The five
DSP core interrupts are SPORT1 receive (or IRQ0) and trans-
mit (or IRQ1), the internal timer, and two software interrupts.
The motor control peripheral interrupts are the nine program-
mable I/Os and two from the PWM (PWMSYNC pulse andPWMTRIP). All motor control interrupts are multiplexed into the
DSP core through the peripheral IRQ2 interrupt. The interrupts
are internally prioritized and individually maskable. A detailed
description of the entire interrupt system of the ADMC326 is
presented later, following a more detailed description of each
peripheral block.
Memory Mapmemory RAM and ROM are provided on the ADMC326. Pro-
gram memory RAM is arranged as one contiguous 512 · 24-bit
block, starting at address 0x0000. Program memory ROM is a
4K · 24-bit block located at address 0x0800. Data memory is
arranged as a 512 · 16-bit block starting at address 0x3800. The
motor control peripherals are memory mapped into a region of
the data memory space starting at 0x2000. The complete program
and data memory maps are given in Tables II and III, respectively.
Table II.Program Memory Map
Table III.Data Memory Map
SYSTEM INTERFACEFigure 4 shows a basic system configuration for the ADMC326
with an external crystal.
33pF
33pFFigure 4.Basic System Configuration
Clock SignalsThe ADMC326 can be clocked either by a crystal or a TTL-
compatible clock signal. For normal operation, the CLKIN
input cannot be halted, changed during operation, or operated
below the specified minimum frequency. If an external clock is
used, it should be a TTL-compatible signal running at half the
instruction rate. The signal is connected to the CLKIN pin of
the ADMC326. In this mode, with an external clock signal, the
XTAL pin must be left unconnected. The ADMC326 uses an
input clock with a frequency equal to half the instruction rate;
a 10 MHz input clock yields a 50 ns processor cycle (which is
equivalent to 20 MHz). Normally, instructions are executed in a
single processor cycle. All device timing is relative to the internal
ADMC326shown in Figure 4. The crystal should be connected across the
CLKIN and XTAL pins, with two capacitors as shown in Figure 4.
A parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used. A clock output signal (CLKOUT) is
generated by the processor at the processor’s cycle rate of twice
the input frequency.
ResetThe ADMC326 DSP core and peripherals must be correctly re-
set when the device is powered up to assure proper initialization.
The ADMC326 contains an integrated power-on reset (POR)
circuit that provides a complete system reset on power-up and
power-down. The POR circuit monitors the voltage on the
ADMC326 VDD pin and holds the DSP core and peripherals in
reset while VDD is less than the threshold voltage level, VRST.
When this voltage is exceeded, the ADMC326 is held in reset
for an additional 216 DSP clock cycles (tRST in Figure 5). On
power-down, when the voltage on the VDD pin falls below
VRST–VHYST, the ADMC326 will be reset. Also, if the externalRESET pin is actively pulled low at any time after power-up, a
complete hardware reset of the ADMC326 is initiated.
VRST
VDD
RESETFigure 5.Power-On Reset Operation
The ADMC326 reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, clears the MSTAT register
and performs a full reset of all of the motor control peripherals.
Following a power-up, it is possible to initiate a DSP core and
motor control peripheral reset by pulling the RESET pin low.
The RESET signal must meet the minimum pulsewidth specifi-
cation, tRSP. Following the reset sequence, the DSP core starts
executing code from the internal PM ROM located at 0x0800.
DSP Control RegistersThe DSP core has a system control register, SYSCNTL, memory
mapped at DM (0x3FFF). SPORT1 is configured as a serial
port when Bit 10 is set, or as flags and interrupt lines when this
bit is cleared. For proper operation of the ADMC326, all other
bits in this register must be cleared.
The DSP core has a wait state control register, MEMWAIT,
memory mapped at DM (0x3FFE). The default value of this
register is 0xFFFF. For proper operation of the ADMC326 this
register must be set to 0x8000.
The configuration of both the SYSCNTL and MEMWAIT
registers of the ADMC326 are shown at the end of this data sheet.
THREE-PHASE PWM CONTROLLER
OverviewThe PWM generator block of the ADMC326 is a flexible, pro-
grammable, three-phase PWM waveform generator that can be
programmed to generate the required switching patterns to drive
patterns for control of electronically commutated motors (ECM)
or brushless dc motors (BDCM).
The PWM generator produces three pairs of active high PWM
signals on the six PWM output pins (AH, AL, BH, BL, CH,
and CL). The six PWM output signals consist of three high side
drive signals (AH, BH, and CH) and three low side drive signals
(AL, BL, and CL). The switching frequency, dead time and
minimum pulsewidths of the generated PWM patterns are pro-
grammable using respectively the PWMTM, PWMDT, and
PWMPD registers. In addition, three registers (PWMCHA,
PWMCHB, and PWMCHC) control the duty cycles of the three
pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the PWM signal destined
for the high side switch is diverted to the complementary low
side output, and the signal destined for the low side switch is
diverted to the corresponding high side output signal.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation tech-
niques: optical isolation using optocouplers, and transformer
isolation using pulse transformers. The PWM controller of the
ADMC326 permits mixing of the output PWM signals with a
high frequency chopping signal to permit an easy interface to
such pulse transformers. The features of this gate-drive chop-
ping mode can be controlled by the PWMGATE register. There
is an 8-bit value within the PWMGATE register that directly
controls the chopping frequency. In addition, high frequency
chopping can be independently enabled for the high side and the
low side outputs using separate control bits in the PWMGATE
register.
The PWM generator is capable of operating in two distinct
modes: single update mode or double update mode. In single
update mode, the duty cycle values are programmable only once
per PWM period, so that the resultant PWM patterns are sym-
metrical about the midpoint of the PWM period. In the double
update mode, a second updating of the PWM duty cycle values
is implemented at the midpoint of the PWM period. In this mode,
it is possible to produce asymmetrical PWM patterns that pro-
duce lower harmonic distortion in three-phase PWM inverters.
This technique also permits the closed-loop controller to change
the average voltage applied to the machine winding at a faster
rate, allowing wider closed-loop bandwidths to be achieved. The
operating mode of the PWM block (single or double update mode)
is selected by a control bit in MODECTRL register.
The PWM generator of the ADMC326 also provides an internal
signal that synchronizes the PWM switching frequency to the
A/D operation. In single update mode, a PWMSYNC pulse is
produced at the start of each PWM period. In double update
mode, an additional PWMSYNC pulse is produced at the mid-
point of each PWM period. The width of the PWMSYNC pulse
is programmable through the PWMSYNCWT register.
The PWM signals produced by the ADMC326 can be shut off
state. Because this hardware shutdown mechanism is asynchro-
nous, and the associated PWM disable circuitry does not use
clocked logic, the PWM will shut down even if the DSP clock is
not running. The PWM system may also be shut down from
software by writing to the PWMSWT register.
Status information about the PWM system of the ADMC326 is
available to the user in the SYSSTAT register. In particular, the
state of PWMTRIP is available, as well as a status bit that indi-
cates whether operation is in the first half or the second half of
the PWM period.
A functional block diagram of the PWM controller is shown in
Figure 6. The generation of the six output PWM signals on pins
AH to CL is controlled by four important blocks:The three-phase PWM timing unit, which is the core of the
PWM controller, generates three pairs of complemented and
dead-time-adjusted center-based PWM signals.The output control unit allows the redirection of the outputs
of the three-phase timing unit for each channel to either the
high side or the low side output. In addition, the output con-
trol unit allows individual enabling/disabling of each of the six
PWM output signals.The GATE drive unit provides the high chopping frequency
and its subsequent mixing with the PWM signals.The PWM shutdown controller manages the three PWM
shutdown modes (via the PWMTRIP pin, the analog block or
the PWMSWT register) and generates the correct RESET signal
for the Timing Unit.The PWM controller is driven by a clock at the same frequency
as the DSP instruction rate, CLKOUT, and is capable of
generating two interrupts to the DSP core. One interrupt is
generated on the occurrence of a PWMSYNC pulse, and the
other is generated on the occurrence of any PWM shutdown
action.
PWMTRIP
PWM DUTY CYCLE
REGISTERS
PWM CONFIGURATION
REGISTERS
TO INTERRUPT
CONTROLLER
CLKOUT
Three-Phase Timing UnitThe 16-bit three-phase timing unit is the core of the PWM con-
troller and produces three pairs of pulsewidth modulated signals
with high resolution and minimal processor overhead. There are
four main configuration registers (PWMTM, PWMDT, PWMPD
and PWMSYNCWT) that determine the fundamental charac-
teristics of the PWM outputs. In addition, the operating mode
of the PWM (single or double update mode) is selected by Bit 6
of the MODECTRL register. These registers, in conjunction with
the three 16-bit duty cycle registers (PWMCHA, PWMCHB and
PWMCHC), control the output of the three-phase timing unit.
PWM Switching Frequency:PWMTM RegisterThe PWM switching frequency is controlled by the PWM
period register, PWMTM. The fundamental timing unit of
the PWM controller is tCK = 1/fCLKOUT where fCLKOUT is the
CLKOUT frequency (DSP instruction rate). Therefore, for a
20 MHz CLKOUT, the fundamental time increment is 50 ns.
The value written to the PWMTM register is effectively the
number of tCK clock increments in half a PWM period. The
required PWMTM value is a function of the desired PWM
switching frequency (fPWM) and is given by:
Therefore, the PWM switching period, TS, can be written as:
For example, for a 20 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (TS = 100 ms), the correct value
to load into the PWMTM register is:
ADMC326The largest value that can be written to the 16-bit PWMTM
register is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of:
for a CLKOUT frequency of 20 MHz.
PWM Switching Dead Time:PWMDT RegisterThe second important PWM block parameter that must be
initialized is the switching dead time. This is a short delay time
introduced between turning off one PWM signal (for example
AH) and turning on its complementary signal, AL. This short
time delay is introduced to permit the power switch being turned
off to completely recover its blocking capability before the
complementary switch is turned on. This time delay prevents a
potentially destructive short-circuit condition from developing
across the dc link capacitor of a typical voltage source inverter.
Dead time is controlled by the PWMDT register. The dead
time is inserted into the three pairs of PWM output signals. The
dead time, TD, is related to the value in the PWMDT register by:
Therefore, a PWMDT value of 0x00A (= 10), introduces a 1 ms
delay between the turn-off of any PWM signal (for example AH)
and the turn-on of its complementary signal (AL). The amount
of the dead time can therefore be programmed in increments of
2 tCK (or 100 ns for a 20 MHz CLKOUT). The PWMDT register
is a 10-bit register. For a CLKOUT rate of 20 MHz its maximum
value of 0x3FF (= 1023) corresponds to a maximum programmed
dead time of:
TDmax= 1023 · 2 · tCK
= 1023 · 2 · 50 · 10–9 sec
= 102 ms
The dead time can be programmed to zero by writing 0 to the
PWMDT register.
PWM Operating Mode:MODECTRL and SYSSTAT RegistersThe PWM controller of the ADMCF326 can operate in two dis-
tinct modes: single update mode and double update mode. The
operating mode of the PWM controller is determined by the
state of Bit 6 of the MODECTRL register. If this bit is cleared, the
PWM operates in the single update mode. Setting Bit 6 places
the PWM in the double update mode. By default, following
either a peripheral reset or power-on, Bit 6 of the MODECTRL
register is cleared. This means that the default operating mode
is single update mode.
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks
the start of a new PWM cycle and is used to latch new values
from the PWM configuration registers (PWMTM, PWMDT,
PWMPD and PWMSYNCWT) and the PWM duty cycle
registers (PWMCHA, PWMCHB and PWMCHC) into the
three-phase timing unit. The PWMSEG register is also latched
into the output control unit on the rising edge of the PWMSYNC
pulse. In effect, this means that the parameters of the PWM
In double update mode, there is an additional PWMSYNC pulse
produced at the midpoint of each PWM period. The rising edge
of this new PWMSYNC pulse is again used to latch new values
of the PWM configuration registers, duty cycle registers and the
PWMSEG register. As a result, it is possible to alter both the
characteristics (switching frequency, dead time, minimum pulse-
width and PWMSYNC pulsewidth) and the output duty cycles
at the midpoint of each PWM cycle. Consequently, it is pos-
sible to produce PWM switching patterns that are no longer
symmetrical about the midpoint of the period (asymmetrical
PWM patterns).
In the double update mode, operation in the first half or the
second half of the PWM cycle is indicated by Bit 3 of the
SYSSTAT register. In double update mode, this bit is cleared
during operation in the first half of each PWM period (between
the rising edge of the original PWMSYNC pulse and the rising
edge of the new PWMSYNC pulse, which is introduced in
double update mode). Bit 3 of the SYSSTAT register is set
during the second half of each PWM period. If required, a user
may determine the status of this bit during a PWMSYNC inter-
rupt service routine.
The advantages of the double update mode are that lower har-
monic voltages can be produced by the PWM process and wider
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Because new duty cycle values
must be computed in each PWMSYNC interrupt service routine,
there is a larger computational burden on the DSP in the double
update mode.
Width of the PWMSYNC Pulse: PWMSYNCWT RegisterThe PWM controller of the ADMCF326 produces an internal
PWM synchronization pulse at a rate equal to the PWM switching
frequency in single update mode and at twice the PWM frequency
in the double update mode. This PWMSYNC synchronizes
the operation of the PWM unit with the A/D converter system.
The width of this PWMSYNC pulse is programmable by the
PWMSYNCWT register. The width of the PWMSYNC pulse,
TPWMSYNC, is given by:
which means that the width of the pulse is programmable from tCK
to 256 tCK (corresponding to 50 ns to 12.8 ms for a CLKOUT rate
of 20 MHz). Following a reset, the PWMSYNCWT register con-
tains 0x27 (= 39) so that the default PWMSYNC width is 2.0 ms.
PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC
RegistersThe duty cycles of the six PWM output signals are controlled
by the three duty cycle registers, PWMCHA, PWMCHB, and
PWMCHC. The integer value in the register PWMCHA controls
the duty cycle of the signals on AH and AL. PWMCHB controls
the duty cycle of the signals on BH and BL, and PWMCHC
controls the duty cycle of the signals on CH and CL. The duty
cycle registers are programmed in integer counts of the funda-
mental time unit, tCK, and define the desired on-time of the
high-side PWM signal produced by the three-phase timing unit
over half the PWM period. The switching signals produced by
The PWM is center-based. This means that in single update mode
the resulting output waveforms are symmetrical and centered in
the PWMSYNC period. Figure 7 presents a typical PWM tim-
ing diagram illustrating the PWM-related registers’ (PWMCHA,
PWMTM, PWMDT, and PWMSYNCWT) control over the
waveform timing in both half cycles of the PWM period. The
magnitude of each parameter in the timing diagram is determined
by multiplying the integer value in each register by tCK (typically
50 ns). It may be seen in the timing diagram how dead time is
incorporated into the waveforms by moving the switching edges
away from the instants set by the PWMCHA register.
PWMSYNC
SYSSTAT (3)Figure 7.Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode
Each switching edge is moved by an equal amount (PWMDT tCK) to preserve the symmetrical output patterns. The PWMSYNC
pulse, whose width is set by the PWMSYNCWT register, is also
shown. Bit 3 of the SYSSTAT register indicates which half cycle
is active. This can be useful in double update mode, as will be
discussed later.
The resultant on-times of the PWM signals shown in Figure 7
may be written as:
The corresponding duty cycles are:
Obviously, negative values of TAH and TAL are not permitted
because the minimum permissible value is zero, corresponding
to a 0% duty cycle. In a similar fashion, the maximum value is
TS, corresponding to a 100% duty cycle.
The output signals from the timing unit for operation in double
update mode are shown in Figure 8. This illustrates a completely
general case where the switching frequency, dead time and duty
cycle are all changed in the second half of the PWM period. Of
course, the same value for any or all of these quantities could be
used in both halves of the PWM cycle. However, it can be seen
that there is no guarantee that symmetrical PWM signals will be
produced by the timing unit in this double update mode. Addi-
Figure 8.Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode
In general, the on-times of the PWM signals in double update
mode are defined by:
TAH = (PWMCHA1 + PWMCHA2 – PWMDT1
– PWMDT2 ) · tCK
TAL = (PWMTM1 + PWMTM2 – PWMCHA1
– PWMCHA2 – PWMDT1 – PWMDT2) · tCK
where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
because for the completely general case in double update mode,
the switching period is given by:
TS = (PWMTM1 + PWMTM2) · tCK
Again, the values of TAH and TAL are constrained to lie between
zero and TS.
PWM signals similar to those illustrated in Figure 7 and Figure
8 can be produced on the BH, BL, CH, and CL outputs by pro-
gramming the PWMCHB and PWMCHC registers in a manner
identical to that described for PWMCHA.
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
ADMC326after the PWMCHA, PWMCHB, and PWMCHC registers,
then the first PWMSYNC pulse (and interrupt if enabled) will
be generated (1.5 · tCK · PWMTM) seconds after the initial
write to the PWMTM register in single update mode. In double
update mode, the first PWMSYNC pulse will be generated
(tCK · PWMTM) seconds after the initial write to the PWMTM
register in single update mode.
Effective PWM ResolutionIn single update mode, the same values of PWMCHA, PWMCHB
and PWMCHC are used to define the on-times in both half
cycles of the PWM period. As a result, the effective resolution of
the PWM generation process is 2 tCK (or 100 ns for a 20MHz
CLKOUT) since incrementing one of the duty cycle registers by
one changes the resultant on-time of the associated PWM sig-
nals by tCK in each half period (or 2 tCK for the full period).
In double update mode, improved resolution is possible since
different values of the duty cycles registers are used to define the
on-times in both the first and second halves of the PWM period.
As a result, it is possible to adjust the on-time over the whole
period in increments of tCK. This corresponds to an effective
PWM resolution of tCK in double update mode (or 50 ns for a
20 MHz CLKOUT).
The achievable PWM switching frequency at a given PWM
resolution is tabulated in Table IV.
Table IV.Achievable PWM Resolution in Single and Double
Update Modes
Minimum Pulsewidth:PWMPD RegisterIn many power converter switching applications, it is desirable
to eliminate PWM switching pulses shorter than a certain width.
It takes a finite time to both turn on and turn off modern power
semiconductor devices. Therefore, if the width of any of the PWM
pulses is shorter than some minimum value, it may be desirable to
completely eliminate the PWM switching for that particular cycle.
The allowable minimum on-time for any of the six PWM out-
puts for half a PWM period that can be produced by the PWM
controller may be programmed using the PWMPD register. The
minimum on-time is programmed in increments of tCK so that
the minimum on-time that will be produced for any half PWM
period, TMIN, is related to the value in the PWMPD register by:
TMIN = PWMPD · tCK
A PWMPD value of 0x002 defines a permissible minimum
on-time of 100 ns for a 20 MHz CLKOUT.
In each half cycle of the PWM, the timing unit checks the on-
time of each of the six PWM signals. If any of the times is found
to be less than the value specified by the PWMPD register, the
while operating in single update mode. For this case, the PWM
switching frequency is 50 kHz and the dead time is 300 ns. The
minimum permissible on-time of any PWM signal over one-half
of any period is 500 ns. Clearly, for this example, the dead-time
adjusted on-time of the AH signal for one-half a PWM period is
(5–3) · 50 ns = 100 ns. Because this is less than the minimum
permissible value, output AH of the timing unit will remain
OFF (0% duty cycle). Additionally, the AL signal will be turned
ON for the entire half period (100% duty cycle).
Output Control Unit: PWMSEG RegisterThe operation of the output control unit is managed by the 9-bit
read/write PWMSEG register. This register sets two distinct
features of the output control unit that are directly useful in the
control of ECM or BDCM.
The PWMSEG register contains three crossover bits, one for each
pair of PWM outputs. Setting Bit 8 of the PWMSEG register
enables the crossover mode for the AH/AL pair of PWM signals;
setting Bit 7 enables crossover on the BH/BL pair of PWM signals;
and setting Bit 6 enables crossover on the CH/CL pair of PWM
signals. If crossover mode is enabled for any pair of PWM signals,
the high-side PWM signal from the timing unit (for example
AH) is diverted to the associated low-side output of the output
control unit so that the signal will ultimately appear at the AL
pin. Of course, the corresponding low-side output of the timing
unit is also diverted to the complementary high-side output of
the output control unit so that the signal appears at Pin AH.
Following a reset, the three crossover bits are cleared so that the
crossover mode is disabled on all three pairs of PWM signals.
The PWMSEG register also contains six bits (Bits 0 to 5) that
can be used to individually enable or disable each of the six PWM
outputs. If the associated bit of the PWMSEG register is set,
the corresponding PWM output is disabled regardless of the
value of the corresponding duty cycle register. This PWM output
signal will remain in the OFF state as long as the corresponding
enable/disable bit of the PWMSEG register is set. The PWM
output enable function gates the crossover function. After a
reset, all six enable bits of the PWMSEG register are cleared,
thereby enabling all PWM outputs by default.
In a manner identical to the duty cycle registers, the PWMSEG is
latched on the rising edge of the PWMSYNC signal so that changes
to this register only become effective at the start of each PWM
cycle in single update mode. In double update mode, the PWM-
SEG register can also be updated at the midpoint of the PWM cycle.
In the control of an ECM, only two inverter legs are switched
at any time, and often the high-side device in one leg must be
switched ON at the same time as the low-side driver in a second
leg. Therefore, by programming identical duty cycles for two PWM
channels (for example, let PWMCHA = PWMCHB) and setting
Bit 7 of the PWMSEG register to crossover the BH/BL pair of
PWM signals, it is possible to turn ON the high-side switch of
Phase A and the low-side switch of Phase B at the same time. In
the control of an ECM, one inverter leg (Phase C in this example)
is disabled for a number of PWM cycles. This disable may be
implemented by disabling both the CH and CL PWM outputs
by setting Bits 0 and 1 of the PWMSEG register. This is illus-
trated in Figure 9 where it can be seen that both the AH and
For the situation illustrated in Figure 9, the appropriate value
for the PWMSEG register is 0x00A7. In ECM operation, be-
cause each inverter leg is disabled for certain periods of time,
the PWMSEG register is changed based upon the position of
the rotor shaft (motor commutation).
PWMCHA
= PWMCHB
PWMCHA
= PWMCHBFigure 9. An example of PWM signals suitable for ECM
control. PWMCHA = PWMCHB, BH/BL are a crossover pair.
AL, BH, CH and CL outputs are disabled. Operation is in
single update mode.
Gate Drive Unit: PWMGATE RegisterThe gate drive unit of the PWM controller adds features that
simplify the design of isolated gate drive circuits for PWM
inverters. If a transformer-coupled power device gate drive
amplifier is used, the active PWM signal must be chopped at
a high frequency. The PWMGATE register allows the program-
ming of this high frequency chopping mode. The chopped active
PWM signals may be required for the high-side drivers only, for
the low-side drivers only, or for both the high-side and low-side
switches. Therefore, independent control of this mode for both
high- and low-side switches is included with two separate con-
trol bits in the PWMGATE register.
Typical PWM output signals with high-frequency chopping
enabled on both high-side and low-side signals are shown in
Figure 10. Chopping of the high-side PWM outputs (AH, BH,
and CH) is enabled by setting Bit 8 of the PWMGATE register.
Chopping of the low-side PWM outputs (AL, BL, and CL) is
enabled by setting Bit 9 of the PWMGATE register. The high
chopping frequency is controlled by the 8-bit word (GDCLK)
written to Bits 0 to 7 of the PWMGATE register. The period
and the frequency of this high frequency carrier are:
The GDCLK value may range from 0 to 255, corresponding
to a programmable chopping frequency rate from 19.5 kHz to
5 MHz for a 20 MHz CLKOUT rate. The gate drive features
must be programmed before operation of the PWM controller
Figure 10.Typical PWM signals with high frequency gate
chopping enabled on both high-side and low-side switches
(GDCLK is the integer equivalent of the value in Bits 0 to 7
of the PWMGATE register.)
PWM ShutdownIn the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down. Two methods of
sensing a fault condition are provided by the ADMC326. For
the first method, a low level on the PWMTRIP pin initiates an
instantaneous, asynchronous (independent of DSP clock) shut-
down of the PWM controller. This places all six PWM outputs in
the OFF state, disables the PWMSYNC pulse and associated
interrupt signal and generates a PWMTRIP interrupt signal.
The PWMTRIP pin has an internal pull-down resistor so that
even if the pin becomes disconnected, the PWM outputs will be
disabled. The state of the PWMTRIP pin can be read from
Bit 0 of the SYSSTAT register.
The second method for detecting a fault condition is through
the ISENSE pin in the analog block of the ADMC326. The ISENSE
pin monitors the feedback signals from a dc bus current sensing
resistor that represents the total current in the motor. When the
voltage of ISENSE goes below ISENSE trip threshold, PWMTRIP
will be internally pulled low. The negative edge of the internalPWMTRIP will generate a shutdown in the same manner as a
negative edge on pin PWMTRIP.
It is possible through software to initiate a PWM shutdown by
writing to the 1-bit read/write PWMSWT register (0x2061).
Writing to this bit generates a PWM shutdown in a manner
identical to the PWMTRIP or ISENSE pins. Following a PWM
shutdown, it is possible to determine if the shutdown was gener-
ated from hardware or software by reading the same PWMSWT
register. Reading this register also clears it.
Restarting the PWM after a fault condition is detected requires
clearing the fault and reinitializing the PWM. Clearing the fault
requires that PWMTRIP returns to a HI state and ISENSE returns
to a voltage greater than the ISENSE trip threshold. After the fault
has been cleared, the PWM can be restarted by writing to registers
PWMTM, PWMCHA, PWMCHB and PWMCHC. After the fault
is cleared and the PWM registers are initialized, internal timing
of the three-phase timing unit will resume, and the new duty cycle
values will be latched on the next rising edge of PWMSYNC.
PWM RegistersThe configuration of the PWM registers is described at the end
of the data sheet. The parameters of the 16-bit PWM Timer is
tabulated in Table V.
ADC OVERVIEWThe ADC of the ADMC326 is based upon the single slope
ADMC326
Table VI.ADC Auxiliary Channel SelectionThe single slope technique has been adapted on the ADMC326
for four channels that are simultaneously converted. Refer to
Figure 11 for the functional schematic of the ADC. Three of the
main inputs (V1, V2, and V3) are directly connected as high
impedance voltage inputs. The fourth channel has been con-
figured with a serially-connected 4-to-1 multiplexer. Table VI
shows the multiplexer input selection codes. One of these auxiliary
multiplexed channels is used to calibrate the ramp against the
internal voltage reference (VREF).
PWMSYNC (CONVST)
(CAP RESET)
CLK MODECTRL<7>
VREF
GNDFigure 11.ADC Overview
Comparing each ADC input to a reference ramp voltage, and tim-
ing the comparison of the two signals, performs the conversion
process. The actual conversion point is the time point intersec-
Table V.Fundamental Characteristics of PWM Generation Unit of ADMC326
16-BIT PWM TIMERProgrammable Dead Time Increments
Programmable Pulse Deletion Range
Programmable Pulse Deletion Increments
PWM Frequency Range
PWMSYNC Pulsewidth (TCRST)
fixed current into an off-chip capacitor, where the capacitor
voltage is
VC = (I/C) · t
Following reset, VC = 0 at t = 0. This reset and the start of the
conversion process are initiated by the PWMSYNC pulse, as
shown in Figure 12. The width of the PWMSYNC pulse is
controlled by the PWMSYNCWT register and should be
programmed according to Figure 13 to ensure complete resetting.
In order to compensate for IC process manufacturing tolerances
(and to adjust for capacitor tolerances), the current source of the
ADMC326 is software programmable. The software setting of the
magnitude of the ICONST current generator is accomplished by
selecting one of eight steps over an approximately 20% cur-
rent range.
PWMSYNC
VVIL
COMPARATOR
OUTPUTFigure 12.Analog Input Block Operation
The ADC system consists of four comparators and a single timer,
which may be clocked at either the DSP rate or half the DSP
rate depending on the setting of the ADCCNT bit (Bit 7) of the
MODECTRL register. When this bit is cleared, the timers count
at a slower rate of CLKIN. When this bit is set, they count at
CLKOUT or twice the rate of CLKIN. ADC1, ADC2, ADC3,
