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ADM1232AARWADN/a27avaiMicroprocessor Supervisory Circuit


ADM1232AARW ,Microprocessor Supervisory CircuitSpecifications subject to change without notice.REV. 0–2–ADM1232AABSOLUTE MAXIMUM RATINGS* RM-8(T = ..
ADM1232AN ,Microprocessor Supervisory CircuitSpecifications subject to change without notice.REV. B–2–ADM1232ABSOLUTE MAXIMUM RATINGS* RM-8(T = ..
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ADM1232ARW ,Microprocessor Supervisory CircuitFEATURES FUNCTIONAL BLOCK DIAGRAMSuperior Upgrade for MAX1232 and Dallas DS1232Low Power Consumptio ..
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ADM1232AARW
Microprocessor Supervisory Circuit
REV.0
Microprocessor
Supervisory Circuit
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Superior Upgrade for MAX1232 and Dallas DS1232
Low Power Consumption (500 mA max)
Adjustable Precision Voltage Monitor with +4.5 V and
+4.75 V Options
Adjustable STROBE Monitor with 150 ms, 600 ms or
1.2 sec Options
No External Components
Fast (20 ns) Strobe Pulsewidth
APPLICATIONS
Microprocessor Systems
Portable Equipment
Computers
Controllers
Intelligent Instruments
Automotive Systems
Protection Against Damage Caused by mP Failure
GENERAL DESCRIPTION

The ADM1232A is a superior, pin-compatible upgrade for the
MAX1232 and the DS1232LP and DS1232. The ADM1232A
can detect strobe pulsewidths as narrow as 20ns, making it
compatible with high speed microprocessors. The Analog
Devices ADM1232A is a microprocessor monitoring circuit
that can monitor:Microprocessor Supply Voltage.Whether a Microprocessor has locked up.An External Interrupt.
The ADM1232A is available in four different packages:The ADM1232AARM in an 8-lead mSOIC (RM-8).The ADM1232AAN in an 8-lead PDIP (N-8).The ADM1232AARW in a 16-lead wide SOIC (R-16).The ADM1232AARN is an 8-lead narrow SOIC (R-8).
Figure 1.Typical Supply Monitoring Application
ADM1232A–SPECIFICATIONS(VCC = Full Operating Range, TA = TMIN to TMAX unless otherwise noted)
STROBE AND PB RESET INPUTS
1 V OPERATION
VCC TRIP POINT
VCC FAIL DETECT TO RESET OUTPUT DELAY
Specifications subject to change without notice.
ORDERING GUIDE
*N = Plastic DIP; R = Small Outline; RM = mSOIC.
ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . .–0.3 V to VCC + 0.3 V
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
N-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Derate by 13.5 mW/°C above 25°CJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .100°C/W
R-16

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .900 mW
Derate by 12 mW/°C above 25°CJA Thermal Impedance (Still Air) . . . . . . . . . . . . . .73°C/W
RM-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .900 mW
Derate by 12 mW/°C above 25°CJA Thermal Impedance (Still Air) . . . . . . . . . . . . .206°C/W
R-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . .900 mW
Derate by 12 mW/°C above 25°CJA Thermal Impedance (Still Air) . . . . . . . . . . . . .153°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM1232A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ADM1232A
PIN FUNCTION DESCRIPTIONS

RESET
STROBE
PIN CONFIGURATIONS
R-16
NC = NO CONNECT
TOLERANCE
GND
PB RESET
STROBE
RESET
RESET
VCC
N-8 and R-8
RM-8
PB RESET
RESET
STROBE
VCC
TOLERANCE
GND
RESET
STROBE Timeout Selection
TD or time delay set is used to set the Strobe Timeout Period.
The Strobe Timeout Period is defined as being the maximum
time between high-to-low transitions (Figure 4) that STROBE
will accept before a reset will be asserted. The Strobe timeout
settings are listed in Table I.
Table I.
STROBE TIMEOUT PERIOD
STROBE
STROBE
PULSEWIDTH

Figure 4.STROBE Parameters
Figure 5.Reset Output Delay
TOLERANCE

The TOLERANCE input is used to determine the level VCC can
vary below 5 V without the ADM1232A asserting a reset. Con-
necting TOLERANCE to ground will select a –5% tolerance
level and will cause the ADM1232A to generate a reset if VCC
falls below 4.75 V (typical). If TOLERANCE is connected to
VCC a –10% tolerance level is selected and will cause the
ADM1232A to generate a reset if VCC falls below 4.5 V (typical).
Check the parameters for the VCC trip point in the ADM1232A
Specifications for more information.
RESET AND RESET OUTPUTS

While RESET is capable of sourcing and sinking current,
RESET is an open drain MOSFET which sinks current only.
Therefore, it is necessary to pull this output high.
CIRCUIT INFORMATION
PB RESET

The PB RESET input makes it possible to manually reset a system
using either a standard push-button switch or a logic low
input. An internal debounce circuit provides glitch immunity
when used with a switch, reducing the effects of glitches on the
line. The debounce circuit is guaranteed to cause the ADM1232A
to assert a reset if PB RESET is brought low for more than 20 ms
and is guaranteed to ignore low inputs of less than 1 ms.
VCC

Figure 2.Typical Push Button Reset Application
RESET
RESET
PB RESET

Figure 3.PB RESET
C3421–8–7/99
PRINTED IN U.S.A.
ADM1232A
OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).
16-Lead Wide SOIC
(R-16)
0.4193 (10.65)0.3937 (10.00)0.2914 (7.40)
PIN 1
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
0.0291 (0.74)
0.0098 (0.25)
3 458
8-Lead mSOIC
(RM-8)51
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
0.120 (3.05)
0.112 (2.84)
8-Lead PDIP
(N-8)
PIN 1
SEATING
PLANE0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)0.210 (5.33)
MAX0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
8-Lead Narrow SOIC
(R-8)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.102 (2.59)
0.094 (2.39)
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
0.0196 (0.50)
0.0099 (0.25)
3 458
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