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ADG221BQADN/a2avaiLC2MOS QUAD SPST SWITCHES
ADG221KNN/a41avaiLC2MOS QUAD SPST SWITCHES
ADG221KPADN/a18avaiLC2MOS QUAD SPST SWITCHES
ADG221KRN/a5avaiLC2MOS QUAD SPST SWITCHES
ADG221KRADN/a300avaiLC2MOS QUAD SPST SWITCHES
ADG222BQADN/a3avaiLC2MOS QUAD SPST SWITCHES
ADG222KNADN/a96avaiLC2MOS QUAD SPST SWITCHES
ADG222KPADN/a139avaiLC2MOS QUAD SPST SWITCHES
ADG222KRADN/a52avaiLC2MOS QUAD SPST SWITCHES
ADG222TQADN/a1avaiLC2MOS QUAD SPST SWITCHES


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ADG222BQ ,LC2MOS QUAD SPST SWITCHESGENERAL DESCRIPTION The ADG221 and ADG222 are monolithic CMOS devices com- prising four indepen ..
ADG222KN ,LC2MOS QUAD SPST SWITCHESFEATURES 44V Supply Maximum Rating * 15V Analog Signal Range Low Ron (600.) Low Leakage ..
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AF216M245001-T , CHIP ANTENNA


ADG221BQ-ADG221KN-ADG221KP-ADG221KR-ADG222BQ-ADG222KN-ADG222KP-ADG222KR-ADG222TQ
LC2MOS QUAD SPST SWITCHES
ANALOG
DEVICES,
Quad SPST Switches
ADGZZI/ADGZZZ
FEATURES
44V Supply Maximum Rating
' 15V Analog Signal Range
Low Row (60n)
Low Leakage (0.5nA)
Break-Before-Make Switching
Extended Plastic Temperature Range
(-40°C to +85°C)
Low Power Dissipation (25.5mW)
wp, TTL, CMOS Compatible
Available in 16-Lead DlP/SOIC and
20-Lead PLCC/LCCC Packages
Surface Mount Packages
Superior DG221 Replacement
GENERAL DESCRIPTION
The ADG221 and ADG222 are monolithic CMOS devices com-
prising four independently selectable switches. On-chip latches
facilitate microprocessor interfacing. They are designed on an
enhanced LCZMOS process which gives an increased signal
handling capability of t. 15V. These switches also feature high
switching speeds and low Ros.
The ADG221 and ADG222 consist of four SPST switches. They
differ only in that the digital control logic is inverted. All devices
exhibit break before make switching action. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
REGULATOR
l L 9 S1
INI G -- - - -
sc-,, DI
f__0 S2
1N2 G- . -- - il
INPUT -o D2
r,--<' S3
IN3 G ----- il
r,---' S4
m4 G ----i/
-- l o D4
WR o- ADG221
ADG222
PRODUCT HIGHLIGHTS
Easily Interfaced:
Digital inputs are latched with a W signal for microprocessor
interfacing. A 5V regulated supply is internally generated
permitting wider tolerances on the supplies without affecting
the TTI. digital input switching levels.
. Single Supply Operation:
For applications where the analog signal is unipolar (0V to
15V), the switches can be operated from a single +15V
supply.
Low Leakage:
Leakage currents in the range of SOOpA make these switches
suitable for high precision circuits. The added feature of
Break-before-Make switching allows for multiple outputs to
be tied together for multiplexer applications while keeping
leakage errors to a minimum.
ADG221 ADG222 SWITCH
W IN IN CONDITION
0 0 1 ON
0 1 0 OFF
1 X X Retains Previous
Switch Condition
Table /. Truth Table
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Telex: 924491
Fax: 617/326-8703
wa: 710/394-6577
Cable: ANALOG NORWOODMASS
Al%Zl1/lllMflfl - SPECIFICATIONS (Van = +15ll, Ilss = -15ll, unless otherwise specified)
K Version B Version T Version
- 40''C to - 40°C to - 55°C to
Parameter 25''C + 85''C 25°C + 85°C 25°C + 125°C Units Test Conditions
ANALOG SWITCH
Analog Signal Range :15 :15 :15 t 15 t 15 t 15 Volts
RON 60 60 60 n typ -10VssNssa + 10V
90 145 90 145 90 145 n max los - 1.0mA
Test Circuit 1
RON vs. Vo (Vs) 20 20 20 % typ
Ros Drift 0.5 0.5 0.5 %/°C typ
Ros Match 5 5 5 % typ VS = 0V, los = 1mA
Is (OFF) 0.5 0.5 0.5 nA typ VD: tl4V;Vs i 14V;TestCircuit2
OFF Input Leakage 2 100 2 100 1 100 nA max
ID(OFF) 0.5 0.5 0.5 nAlyp VD: tl4V;Vs= T14V;TestCircuit2
OFF Output Leakage 2 100 2 100 1 100 nA max
ID(ON) 0.5 0.5 0.5 nA typ VI) = A 14V;Tcst Circuit3
ON Channel Leakage 2 200 2 200 l 200 nA max
DIGITAL CONTROL
Vom, Input High Voltage 2.4 2.4 2.4 V min
VINL, Input Low Voltage 0.8 0.8 0.8 V max
IINL or IINH 1 l l " max
DYNAMIC CHARACTERISTICS
toees 30 30 30 ns typ
IONI 300 300 300 ns max Test Circuit 4
tor-sl 250 250 250 ns max TestCircuit 4
twt Write Pulse Width 100 100 100 120 ns min See Figure 2
tsl Digital Input Setup Time 100 100 100 120 ns min See Figure 2
tul Digital Input Hold Time 20 20 20 20 ns min See Figure 2
OFF Isolation 80 80 80 dB typ Vs -, IOV (p-p); l: lOOkHz
RL - 750; Test Circuit 6
Channel-to-Channel Crosstalk 80 80 80 dB typ Test Circuit 7
Cs (OFF) 5 5 5 pF typ
CD (OFF) 5 5 5 pF typ
CD,CS(ON) 16 l6 l6 thyp
Cm Digital Input Capacitance 5 5 5 pF typ
QINJ Charge Injection 20 20 20 pC typ Rs = on; CL = 1000pF; VS = 0V
Test Circuit 5
POWER SUPPLY
[DD 0.6 0.6 0.6 mAtyp Digital lnputs=V1NL or Vom
Iroro 1.5 1.5 1.5 mAmax
Iss 0.1 0.1 0.1 mAtyp
Iss 0.2 0.2 0.2 mA max
Power Dissipation 25 .5 25.5 25.5 mW max
NOTE .
'Sample tested at 25°C to ensure compliai.
tos, tore are the same for both IN and WR digital input changes.
Specifications subject tochange without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = + 25°C unless otherwise stated)
VDD t0 Vss ........................ 44V Power Dissipation (Any Package)
Voz, to GND ....................... 25V Up to + 75°C .................... 470mW
Vss to GND ....................... - 25V Derates above + 75°C by .............. 6mW/°C
Analog Inputsl Operating Temperature
Voltage at S, D ................ Vss - 0.3V to Commercial (K Version) ......... - 40°C to + 85°C
Vor, + 0.3V Industrial (B Version) ........... - 40°C to + 85°C
Continuous Current, s or D ............. 30mA Extended (T Version) ........... - 55°C to + 125°C
Pulsed Current S or D Storage Temperature ............ - 65°C to + 150°C
lms Duration, 10% Duty Cycle .......... 70mA Lead Temperature (Soldering 10sec) ......... + 300°C
Digital Inputsl
Voltage at IN ., 1‘1’R ............... Vss - 2V to NOTE -
VDD + 2V or lOvervoltage at IN, WR, S or D will be clamped by diodes. Current should be
20mA, Whichever Occurs First
limited to the Maximum Rating above.
'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one Absolute Maximum Rating may be applied at
any one time.
REV. B
h0tylfll/hiel2
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect-
ed; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
ESD SENSITIVE DEVIC
ORDERIN G GUIDE PIN CONFIGURATIONS
Temperature Package
Modell Range Option2 DIP, SOIC
ADG221KN - 40°C to + 85°C N-l6 V
ADGZZIKR - 40°C to + 85°C R-16A IN1 1 q E M2
ADGZZIKP -40T to + 85°C P-20A m E 15 D2
ADG221BQ -40T to + 85°C Q-16 SI 3 E S2
ADGZZITQ - 55°Cto +125°C Q-16 Vss cr 233;; 13 Voo
ADG221TE - 55°C to + 125°C E-20A TOP VIEW -
GND E (Not to Scale) 12 WR
ADG222KN - 40°C to + 85°C N-l6 S4 E 11 S3
ADG222KR - 40°C to + 85°C R-16A
ADG222KP -40oCto + 85°C P-20A D4 E IO D3
ADG222BQ - 40°C to + 85°C Q-16 IN4 CE El IN3
ADG222TQ - 55°C to + 125°C Q-l6
ADG222TE - 55°C to + 125°C E-20A
NOTES LCCC
'To order MIL-STD-883, Class B processed parts, add ISBSB to T grade part
numbers. See Analog Devices Military Products Databook (1990) for
military data sheet.
2N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); P = Plastic
Leaded Chip Carrier (PLCC); Q = Cerdip; E = Leadless Ceramic Chip s, 4 18 S2
Carrier (LCCC). ADG221
Vss 5 2383; 17 Voo ADG222
TOP VIEW
NC 6 TOP VIEW " NC (Not to Scale)
GND 7 (Not to Scale) 15 m
S4 a 14 S3
GENERATOR
Figure 1. Typical Digital InputCell
REV. B
LATCHES
9101112 13
V0 MP)
NC = NO CONNECT
NC = NO CONNECT
TIMING AND CONTROL SEQUENCE
Figure 2 shows the timing sequence for latching the switch
digital inputs (1N1 - 1N4). The latches are level sensitive and,
therefore, while W is held low the latches are transparent and
the switches respond to the digital inputs. The digital inputs are
latched on the rising edge of W.
mM-lN4 X X
3V 1 'e-tw -n' tH -
- , I I
_-ts-----,
tr, - tNt-iN4uaLoTov%HouoTttvtE
ts - ItN_l1-lN4VALlDT0WRSETUPTlME
tw - WR PULSEWIDTH
Figure 2. Timing and Control Sequence
hM221/hlel2---Typiixg Performance Characteristics
The switches are guaranteed functional with reduced single or dual supplies down to 4.5V.
150 T I
VDu=+5V TA=+25°C
Vss= -w
120 / "r,
xo' 'tec-titll'
60 1 ss- --'-cr'"rs
-""ssss., /\~
s-...---'" "ss,,
V =+15V
30 i/2'-rCih', -
-20 -15 -10 -5 0 +5 +10 +15 +20
Vo (Vs) - Volts
RON as a Function of Vo Ns): Dual Supply Voltage
TOO l I l
3232:1133! """
IO - AR J,---""
< 'e""
: In(0N) """ l -"
E r'r'5''" IslOFFrtol0FF) "--""
S 1 - 7/
g ee" "---""
25 35 45 55 65 " 85 95 105 115 125
TEMPERATURE - 'C
Leakage Current as a Function of Temperature (Note:
Leakage Currents Reduce as the Supply Voltages
Reduce)
T, = + 25"C
2 300 -r-
sf, 200 'sss,
"''ss-, tos
torr _---------
z 5 :7 :9 - 11 *13 + 15
SUPPLY VOLTAGE Volts
Switching Times vs. Supply Voltage (Dual Supply)
Tn = + 25"C
am. — n
Vss=0V
-20 -15 -10 -5 0 +5 +10 +15 +20
V0 (V5) - Voks
HON as a Function of Vo Ns): Single Supply Voltage
TA=+25°C
.1 " / / / / f f
u 1,0. _ -
s 7 9 " " "
SUPPLY VOLTAGE - Volts
Trigger Level vs. Power Supply Voltage: Dual or Single
Supply Voltage
T, = + 25°C
g! 200
"'----.,
+ 5 + 7 + 9 + 11 + 13 ' 15
SUPPLY VOLTAGE - Volts
Switching Times vs. Supply Voltage (Single Supply)
REV. B
Test Circuits-Hell/Nell
GD- ls (OFF) ID (OFF)
s o s D
-V1--- ff, 'th, A -Ht""-tt--
;_¥14V :14V -== IolON)
--- VD
! RoN=V1/los
Test Circuit 7 Test Circuit 2 Test Circuit 3
+ 15V 3V
-t- ADG221
V.N 50% 50%
4'13 Vo ul l
I 3 I O 0
IN I _ " 50 /o 50 A,
-‘ R Q7 330il ADG222
Test Circuit 4
'" ----- n Von AD711
as l s D
I l -io"rxr-0
I ' l I v
I vs; I I _ th o _L,
L-- --u to-l WR $1HF 'ro-CL,-,,,.-,'''''
vm GND Vss , 7 QINJ=CL>< AVo
{7 -15v
Test Circuit 5. Charge Injection
+ 15V t- --------- S DO D --___ 75tt
I I r - _____ m - _ y
V00 6 l F
- - S D.--.-.-- shNo---tyo-o'
Ci _ oir- l) - <> Vs
"3; '1: I Tif" a
VIN -tyr--i w“ 72;, f'" ~<% Vm
GND Vss I
----- D s - - - - -
<7 vocr- (rc-r, -- tru-e - __TU‘ -ONC
r,ls,-, RL '
ADG22ING--5V OFFISOLATION = 75it GND Vss
ADG222 v.N = av 20 x LOG Ns/vol I
- - 15V
ADG221 v.N =ov CHANNEL-TO-CHANNEL
ADG222 Vm = 5V CROSSTALK = 20 x LOGNs/1/d
Test Circuit 6. Off Isp/ation Test Circuit 7. Channel-to-Channel Crosstalk
REV B -5-
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