ADF4216BRU Fast Delivery |IC PHOENIX CO.,LIMITED

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ADF4216BRU
Dual, Integer-N 0.5 GHz/1.2 GHz PLL
REV.0
Dual RF PLL Frequency Synthesizers
FUNCTIONAL BLOCK DIAGRAM
CLOCK
DATA
MUXOUTRF
CPIF
REFIN
RFINADD1VDD2VP1VP2
AGNDRFDGNDRFDGNDIFAGNDIF
RFINB
DGNDIF
IFINA
IFINB
FEATURES
ADF4216:550 MHz/1.2 GHz
ADF4217:550 MHz/2.0 GHz
ADF4218:550 MHz/2.5 GHz
2.7 V to 5.5 V Power Supply
Selectable Charge Pump Currents
Selectable Dual Modulus Prescaler
IF:8/9 or 16/17
RF:32/33 or 64/65
3-Wire Serial Interface
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
GENERAL DESCRIPTION
The ADF4216/ADF4217/ADF4218 are dual frequency synthe-
sizers that can be used to implement local oscillators (LOs) in
the upconversion and downconversion sections of wireless
receivers and transmitters. They can provide the LO for both
the RF and IF sections. They consist of a low-noise digital PFD
(Phase Frequency Detector), a precision charge pump, a pro-
grammable reference divider, programmable A and B counters,
and a dual-modulus prescaler (P/P+1). The A (6-bit) and B
(11-bit) counters, in conjunction with the dual modulus prescaler
(P/P+1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R Counter), allows selectable
REFIN frequencies at the PFD input. A complete PLL (Phase-
Locked Loop) can be implemented if the synthesizers are
used with an external loop ﬁlter and VCOs (Voltage Con-
trolled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V
to 5.5 V and can be powered down when not in use.
ADF4216/ADF4217/ADF4218–SPECIFICATIONS1(VDD1 = VDD2 = 3 V � 10%, 5 V � 10%;
VDD1, VDD2 � VP1, VP2 � 6.0 V ; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; TA = TMIN to TMAX unless otherwise noted.)
PHASE DETECTOR
LOGIC INPUTS
LOGIC OUTPUTS
POWER SUPPLIES
ADF4216/ADF4217/ADF4218
POWER SUPPLIES (Continued)
NOTES
1Operating temperature range is as follows: B Version: –40°C to +85°C.The B Chip speciﬁcations are given as typical values.
3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is
less than this value.
4VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels.Guaranteed by design. Sample tested to ensure compliance.
6P = 16; RFIN = 900MHz; IFIN = 540MHz.The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
8The phase noise is measured with the EVAL-ADF421XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the
synthesizer (fREFOUT = 10 MHz @ 0 dBm).
9fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fIF = 540 MHz; N = 2700; Loop B/W = 20 kHz.fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.
11fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop B/W = 3 kHz.fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.
13fREFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.
Speciﬁcations subject to change without notice.
ADF4216/ADF4217/ADF4218
TIMING CHARACTERISTICS
NOTES
Guaranteed by design but not production tested.
Speciﬁcation subject to change without notice.
Figure 1.Timing Diagram
(VDD1 = VDD2 = 3 V � 10%, 5 V � 10%; VP1, VP2 = VDD , 5 V � 10%; AGND = DGND = 0 V;
TA = TMIN to TMAX unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted)
VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB,
IFINA, IFINB to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
11749 (CMOS) and 522 (Bipolar).
ORDERING GUIDE
ADF4217BRU
*Contact the factory for chip availability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4216/ADF4217/ADF4218 features proprietary ESD protection circuitry, permanent
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
ADF4216/ADF4217/ADF4218
–Typical Performance Characteristics
TPC 1.S-Parameter Data for the AD4218 RF Input
(Up to 2.5GHz)
RF INPUT FREQUENCY – GHz211.5–35
RF INPUT POWER
dBm
2.53
TPC 2.Input Sensitivity for the ADF4218 (RF)
TPC 3.ADF4218 RF Phase Noise (900 MHz, 200 kHz, 20 kHz)
TPC 4.ADF4218 RF Reference Spurs (900 MHz, 200 kHz,
20 kHz)
10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 0.55�
100HzFREQUENCY OFFSET FROM 900MHz CARRIER1MHz
PHASE NOISE
dBc/Hz
–140
TPC 5.ADF4218 RF Integrated Phase Noise (900 MHz,
200 kHz, 20 kHz)
TPC 6.ADF4218 RF Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz)
TPC 7.ADF4218 RF Reference Spurs (900 MHz, 200 kHz,
35 kHz)
TPC 8.ADF4218 RF Phase Noise (1750 MHz, 30 kHz, 3 kHz)
10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 1.8�
100HzFREQUENCY OFFSET FROM 1750MHz CARRIER1MHz
PHASE NOISE
dBc/Hz
–140
TPC 9.ADF4218 RF Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)
TPC 10.ADF4218 RF Reference Spurs (1750 MHz,
30 kHz, 3 kHz)
TPC 11.ADF4218 RF Phase Noise vs. PFD Frequency
TPC 12.ADF4218 RF Phase Noise vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
ADF4216/ADF4217/ADF4218
TEMPERATURE – �C
FIRST REFERENCE SPUR
dBc–70
–20
TPC 13.ADF4218 RF Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
TPC 14.ADF4218 RF Reference Spurs vs. VTUNE (900 MHz,
200 kHz, 20 kHz)
TPC 15.ADF4218 IF Phase Noise (540 MHz, 200 kHz, 20 kHz)
10dB/DIVISIONRL = –40dBc/HzRMS NOISE = 0.52�
100HzFREQUENCY OFFSET FROM 900MHz CARRIER1MHz
PHASE NOISE
dBc/Hz
–140
TPC 16.ADF4218 IF Integrated Phase Noise (540 MHz,
200 kHz, 20 kHz)
TPC 17.ADF4218 IF Reference Spurs (540 MHz, 200 kHz,
20 kHz)
TPC 18.ADF4218 IF Phase Noise vs. PFD Frequency
TEMPERATURE – �C
PHASE NOISE
dBc/Hz
–20
TPC 19.ADF4218 IF Phase Noise vs. Temperature
(540 MHz, 200 kHz, 20 kHz)
TEMPERATURE – �C
FIRST REFERENCE SPUR
dBc–70
–20
TPC 20.ADF4218 IF Reference Spurs vs. Temperature
(540 MHz, 200 kHz, 20 kHz)
TPC 21.ADF4218 IF Reference Spurs vs. VTUNE (900 MHz,
200 kHz, 20 kHz)
TPC 22.DIDD vs. Prescaler Output Frequency (ADF4218,
RF Only)
TPC 23.ADF4218 AIDD vs. Prescaler Value (RF)
ADF4216/ADF4217/ADF4218
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown below in Figure 2. SW1 and
SW2 are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
Figure 2.Reference Input Stage
IF/RF INPUT STAGE
The IF/RF input stage is shown in Figure 3. It is followed by a
2-stage limiting ampliﬁer to generate the CML clock levels
needed for the prescaler.
Figure 3.IF/RF Input Stage
PRESCALER
The dual modulus prescaler (P/P+1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). This prescaler, operating at CML levels, takes
the clock from the IF/RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. It is
based on a synchronous 4/5 core.
The prescaler is selectable. On the IF side it can be set to
either 8/9 (DB20 of the IF AB Counter Latch set to 0) or 16/17
(DB20 set to 1). On the RF side it can be set to 64/65 (DB20 of
the RF AB Counter Latch set to 0) or 32/33 (DB20 set to 1).
See Tables IV and VI.
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
fVCO = [(P × B) + A] × fREFIN/R
fVCO=Output frequency of external voltage controlled oscilla-
tor (VCO).=Preset modulus of dual modulus prescaler (8/9, 16/17,
etc.).=Preset Divide Ratio of binary 11-bit counter (1 to
2047).=Preset Divide Ratio of binary 6-bit A counter (0 to
63).
fREFIN=Output frequency of the external reference frequency
oscillator.=Preset divide ratio of binary 14-bit programmable
reference counter (1 to 16383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase fre-
quency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
Figure 4.A and B Counters
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simpliﬁed schematic.

Partno	Mfg	Dc	Qty	Available	Descript
ADF4216BRU	AD	N/a	5	avai	Dual, Integer-N 0.5 GHz/1.2 GHz PLL