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ADC10DV200CISQ/NOPB |ADC10DV200CISQNOPBNSN/a3avaiDual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs 60-WQFN -40 to 85
ADC10DV200CISQE/NOPB |ADC10DV200CISQENOPBNSN/a3avaiDual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs 60-WQFN -40 to 85


ADC10DV200CISQ/NOPB ,Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs 60-WQFN -40 to 85 SNAS471A –FEBRUARY 2009–REVISED APRIL 2013Pin Descriptions and Equivalent CircuitsPin No. Symbol E ..
ADC10DV200CISQE/NOPB ,Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs 60-WQFN -40 to 85FEATURES DESCRIPTIONThe ADC10DV200 is a monolithic analog-to-digital2• Single 1.8V Power Supply Ope ..
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ADC10DV200CISQ/NOPB-ADC10DV200CISQE/NOPB
Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs
ADC10DV200
www.ti.com
SNAS471A –FEBRUARY 2009–REVISED APRIL 2013
ADC10DV200 Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS
Outputs
Checkfor Samples: ADC10DV200
1FEATURES DESCRIPTION

The ADC10DV200isa monolithic analog-to-digital Single 1.8V Power Supply Operation. converter capable of converting two analog input• Power Scaling with Clock Frequency. signals into 10-bit digital wordsat rates upto 200 Internal Sample-and-Hold. Mega Samples Per Second (MSPS). The digital
output mode is selectable and can be either• Internalor External Reference. differential LVDS or CMOS signals. This converter• Power Down Mode. usesa differential, pipelined architecture with digital• Offset Binaryor 2's Complement Output Data error correction and an on-chip sample-and-hold
Format.
circuitto minimize die size and power consumption
while providing excellent dynamic performance.A• LVDSor CMOS Output Signals. unique sample-and-hold stage yieldsa full-power• 60-pin WQFN Package, (9x9x0.8mm, 0.5mm bandwidth of 900MHz. Fabricated in core CMOSPin-Pitch) process, the ADC10DV200 may be operated froma Clock Duty Cycle Stabilizer. single 1.8V power supply. The ADC10DV200
achieves approximately 9.6 effective bitsat Nyquist• IF Sampling Bandwidth> 900MHz. and consumes just 280mWat 170MSPSin CMOS
mode and 450mWat 200MSPSin LVDS mode. TheKEY SPECIFICATIONS power consumption can be scaled down further by Resolution10 Bits reducing sampling rates. Conversion Rate 200 MSPS ENOB 9.6 bits (typ) @Fin=70 MHz SNR 59.9 dBFS (typ) @Fin=70 MHz SINAD 59.9 dBFS (typ) @Fin=70 MHz SFDR82 dBFS (typ) @Fin=70 MHz LVDS Power 450mW (typ) @Fs=200 MSPS CMOS Power 280mW (typ) @Fs=170 MSPS Operating Temp. Range −40°Cto +85°C.
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