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ADADC80Z-12
12-Bit Successive Approximation Integrated Circuit A/D Converter
REV. D
12-Bit Successive-Approximation
Integrated Circuit A/D Converter
FEATURES
True 12-Bit Operation: Max Nonlinearity �0.012%
Low Gain T.C.: �30 ppm/�C Max
Low Power: 800 mW
Fast Conversion Time: 25 �s
Precision 6.3 V Reference for External Application
Short-Cycle Capability
Parallel Data Output
Monolithic DAC with Scaling Resistors for Stability
Low Chip Count—High Reliability
Industry-Standard Pinout
Z Models for �12 V Supplies
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTIONThe AD ADC80 is a complete 12-bit successive-approximation
analog-to-digital converter that includes an internal clock, refer-
ence, and comparator. Its hybrid IC design uses MSI digital and
linear monolithic chips in conjunction with a 12-bit monolithic
DAC to provide modular performance and versatility with IC
size, price, and reliability.
Important performance characteristics of the AD ADC80 include
a maximum linearity error at 25�C of ±0.012%, maximum gain
T.C. of 30ppm/�C, typical power dissipation of 800 mW, and
maximum conversion time of 25 �s. Monotonic operation of the
feedback D/A converter guarantees no missing codes over the
temperature range of –25�C to +85�C.
The design of the AD ADC80 includes scaling resistors that
provide analog signal ranges of ±2.5 V, ±5.0 V, ±10 V, 0 V to
+5.0 V, or 0 V to +10.0 V. The 6.3 V precision reference may
be used for external applications. All digital signals are fully
DTL and TTL compatible; output data is in parallel form.
The AD ADC80 is available in grades specified for use over
the –25�C to +85�C temperature range and is available in a
32-lead ceramic DIP.
PRODUCT HIGHLIGHTSThe AD ADC80 is a complete 12-bit A/D converter. No
external components are required to perform a conversion.A monolithic 12-bit feedback DAC is used for reduced chip
count and higher reliability.The internal buried Zener reference is laser trimmed to 6.3 V.
The reference voltage is available externally and can supply
up to 1.5 mA beyond that required for the reference and
bipolar offset current.The scaling resistors are included on the monolithic DAC
for exceptional thermal tracking.The AD ADC80 directly replaces other devices of this type,
providing significant increases in performance.The fast conversion rate of the AD ADC80 makes it an
excellent choice for applications requiring high system
throughput rates.The short cycle and external clock options are provided
for applications requiring faster conversion speed or
lower resolution.
The Serial Output function is no longer supported on this product after date
code 9616.
AD ADC80–SPECIFICATIONS(Typical @ 25�C, �15 V, and +5 V, unless otherwise noted.)
AD ADC80TEMPERATURE RANGE
NOTESDTL/TTL compatible, i.e., Logic 0 = 0.8 V max, Logic 1 = 2.0 V min for digital inputs, Logic 0 = 0.4 V max, and Logic 1 = 2.4 V min digital outputs.Adjustable to zero with external trimpots.FSR means full-scale range, i.e., unit connected for ±10 V range has +20 V FSR.Error shown is the same as ±1/2 LSB max for resolution of A/D converter.Conversion time with internal clock.See Table I.CSB—Complementary straight binary
COB—Complementary offset binary
CTC—Complementary twos complementFor conversion speeds specified.For Z models, order AD ADC80Z-12.For package outline information, see Package Information section.
Specifications subject to change without notice.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD ADC80 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ORDERING GUIDE
AD ADC80
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
TPC 1.Linearity Error vs. Conversion Time (Normalized)
TPC 2.Differential Linearity Error vs. Conversion
Time (Normalized)
TPC 3.Maximum Gain Drift Error, % of FSR vs.
Temperature
TPC 4.Reference Drift, % Error vs. Temperature
AD ADC80
THEORY OF OPERATIONOn receipt of a CONVERT START command, the AD ADC80
converts the voltage at its analog input into an equivalent 12-bit
binary number. This conversion is accomplished as follows: the
12-bit successive-approximation register (SAR) has its 12-bit
outputs connected both to the device bit output pins and to the
corresponding bit inputs of the feedback DAC. The analog input
is successively compared to the feedback DAC output, one bit
at a time (MSB first, LSB last). The decision to keep or reject
each bit is then made at the completion of each bit comparison
period, depending on the state of the comparator at that time.
TIMINGThe timing diagram is shown in Figure 1. Receipt of a CONVERT
START signal sets the STATUS flag, indicating conversion in
progress. This, in turn, removes the inhibit applied to the gated
clock, permitting it to run through 13 cycles. All SAR parallel
bit and STATUS flip-flops are initialized on the leading edge, and
the gated clock inhibit signal is removed on the trailing edge of
the CONVERT START signal. At time t0, B1 is reset and B2–B12
are set unconditionally. At t1, the Bit 1 decision is made (keep)
and Bit 2 is unconditionally reset. At t2, the Bit 2 decision is
made (keep) and Bit 3 is reset unconditionally. This sequence
continues until the Bit 12 (LSB) decision (keep) is made at t12.
After a 40 ns delay period, the STATUS flag is reset, indicating
that the conversion is complete and the parallel output data is
valid. Resetting the STATUS flag restores the gated clock
inhibit signal, forcing the clock output to the Logic 0 state.
Parallel data bits become valid on the positive-going clock edge
(see Figure 1).
Incorporation of this 40 ns delay guarantees that the parallel
data is valid at the Logic l to 0 transition of the STATUS flag,
permitting parallel data transfer to be initiated by the trailing edge
of the STATUS signal.
Figure 1.Timing Diagram (Binary Code 011001110110)
