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AD9925BBCZ
CCD Signal Processor with Vertical Driver and Precision Timing™ Generator
CCD Signal Processor with Vertical Driver
and Precision Timing ™ Generator
Rev. A
FEATURES
Integrated 10-channel V-driver
Register-compatible with the AD9991 and AD9995
3-field (6-phase) vertical clock support
2 additional vertical outputs for advanced CCDs
Complete on-chip timing generator
Precision Timing core with <600 ps resolution
Correlated double sampler (CDS)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
12-bit 36 MHz ADC
Black level clamp with variable level control
On-chip 3 V horizontal and RG drivers
2-phase and 4-phase H-clock modes
Electronic and mechanical shutter support
On-chip driver for external crystal
On-chip sync generator with external sync input
8 mm × 8 mm CSPBGA package with 0.65 mm pitch
APPLICATIONS
Digital still cameras
Digital video camcorders
CCD camera modules
GENERAL DESCRIPTION The AD9925 is a complete 36 MHz front end solution for digi-
tal still camera and other CCD imaging applications. Based on
the AD9995 product, the AD9925 includes the analog front end
and a fully programmable timing generator (AFETG), combined
with a 10-channel vertical driver (V-driver). A Precision Timing
core allows adjustment of high speed clocks with approximately
600 ps resolution at 36 MHz operation.
The on-chip V-driver supports up to 10 channels for use with
3-field (6-phase) CCDs. Two additional vertical outputs can be
used with CCDs that contain advanced video readout modes.
Voltage levels of up to +15 V and −8 V are supported.
The analog front end includes black level clamping, CDS, VGA,
and a 12-bit ADC. The timing generator and V-driver provide
all the necessary CCD clocks: RG, H-clocks, vertical clocks,
sensor gate pulses, substrate clock, and substrate bias control.
The internal registers are programmed using a 3-wire serial
interface.
Packaged in an 8 mm × 8 mm CSPBGA, the AD9925 is speci-
fied over an operating temperature range of −25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
DCLK
MSHUT
STROBE
CLI
DOUT
H1 TO H4
REFTREFB
VSUBVDSYNC
CCDIN
CLO
SDI
SCK
RSTBSUBCK
V1, V2V3A, V3BV4, V6V5A, V5B
V7, V8
Figure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Digital Specifications........................................................................4
Vertical Driver Specifications.........................................................5
Analog Specifications.......................................................................6
Timing Specifications.......................................................................7
Absolute Maximum Ratings............................................................8
Package Thermal Characteristics...............................................8
ESD Caution..................................................................................8
Pin Configuration and Function Descriptions.............................9
Terminology....................................................................................11
Equivalent Circuits.........................................................................12
Typical Performance Characteristics...........................................13
System Overview........................................................................14
Precision Timing High Speed Timing Generation..................15
Horizontal Clamping and Blanking.........................................18
Horizontal Timing Sequence Example....................................21
Vertical Timing Generation......................................................22
Vertical Timing Example...........................................................34
Shutter Timing Control.............................................................36
Example of Exposure and Readout of Interlaced Frame...........41
FG_TRIG Operation..................................................................43
Analog Front End Description and Operation......................45
Vertical Driver Signal Configuration......................................47
Power-Up and Synchronization...............................................51
Standby Mode Operation..........................................................55
Circuit Layout Information.......................................................57
Serial Interface Timing..............................................................59
Complete Listing for Register Bank 1..........................................62
Complete Listing for Register Bank 2..........................................66
Complete Listing for Register Bank 3..........................................87
Outline Dimensions.......................................................................94
Ordering Guide..........................................................................94
REVISION HISTORY
10/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Specifications........................................................................................3
Added Stress Disclaimer..........................................................................................8
Changes to Figure 12................................................................................................13
Changes to Figure 22................................................................................................18
Changes to Figure 55................................................................................................45
Change to DC Restore Section...............................................................................45
Change to Correlated Double Sampler Section....................................................45
Change to ADC Section...........................................................................................46
Change to Digital Data Outputs Section...............................................................46
Added Paragraph to Digital Data Outputs Section..............................................46
Changes to Table 34..................................................................................................55
Change to Circuit Layout Information Section....................................................57
Changes to Register Address Bank 1, Bank 2, and Bank 3 Section...................60
Changes to Table 40..................................................................................................63
Change to Table 46...................................................................................................65
Changes to Tables 47–56, 58–73.............................................................................66
4/04—Revision 0: Initial Version
SPECIFICATIONS
Table 1. The power dissipated by the V-driver circuitry depends on the logic states of the inputs as well as actual CCD operation; default dc values are used for each measure-
ment, in each mode of operation. Load conditions are described in thesection. The total power dissipated by the HVDD supply may be approximated using the equation Total HVDD Power = [CLOAD × HVDD × Pixel Frequency] × HVDD.
Reducing the H-loading and/or using a lower HVDD supply will reduce the power dissipation. CLOAD is the total capacitance seen by all H-outputs.
Vertical Driver Specifications
DIGITAL SPECIFICATIONS RGVDD = HVDD = DVDD = DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.
Table 2. VERTICAL DRIVER SPECIFICATIONS VDVDD = 3.3 V, VH = 15 V, VM = 0 V, VL = −7.5 V, CL shown in load model, 25°C.
Table 3.
V-DRIVER
INPUT
V-DRIVER
OUTPUTtFHM,tFHLtPHL04637-0-079
Figure 2. Definition of V-Driver Timing Specifications
