AD9891KBC ,CCD Signal Processor with Precision Timing™ GeneratorOVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Input Clamp . . . . . . . . . . ..
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ADSP-21266SKBCZ-2B , SHARC Embedded Processor
ADSP-21266SKBCZ-2B , SHARC Embedded Processor
ADSP-21266SKSTZ-1B , SHARC Embedded Processor
AD9891KBC
CCD Signal Processor with Precision Timing™ Generator
REV. A
CCD Signal Processors with
Precision Timing™ GeneratorPxGA is a registered trademark and Precision Timing is a trademark of Analog Devices, Inc.
FEATURES
AD9891: 10-Bit 20 MHz Version
AD9895: 12-Bit 30 MHz Version
Correlated Double Sampler (CDS)
4 �6 dB Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 20 MHz A/D Converter (AD9891)
12-Bit 30 MHz A/D Converter (AD9895)
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Generator
Precision Timing Core with 1 ns Resolution
On-Chip 5 V Horizontal and RG Drivers
2-Phase and 4-Phase H-Clock Modes
4-Phase Vertical Transfer Clocks
Electronic and Mechanical Shutter Modes
On-Chip Driver for External Crystal
On-Chip Sync Generator with External Sync Option
64-Lead CSPBGA Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
FUNCTIONAL BLOCK DIAGRAM
DCLK
CLPOB/PBLK
FD/LD
MSHUT
STROBE
CLO
CLI
DOUT
H1–H4
V1–V4
VSG1–VSG8
VRTVRB
VSUBSUBCKHDVDSYNCSCKDATA
CCDIN
PRODUCT DESCRIPTIONThe AD9891 and AD9895 are highly integrated CCD signal
processors for digital still camera applications. Both include a
complete analog front end with A/D conversion combined with
a full-function programmable timing generator. A Precision
Timing core allows adjustment of high speed clocks with 1ns
resolution at 20MHz operation and 700 ps resolution at 30
MHz operation.
The AD9891 is specified at pixel rates of up to 20MHz, and
the AD9895 is specified at 30 MHz. The analog front end
includes black level clamping, CDS, PxGA, VGA, and a 10-Bit
or 12-Bit A/D converter. The timing generator provides all the
necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control. Operation is
programmed using a 3-wire serial interface.
Packaged in a space-saving 64-lead CSPBGA, the AD9891 and
AD9895 are specified over an operating temperature range of
–20°C to +85°C.
AD9891/AD9895
TABLE OF CONTENTSSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . .3
AD9891 ANALOG SPECIFICATIONS . . . . . . . . . . . . . .4
AD9895 ANALOG SPECIFICATIONS . . . . . . . . . . . . . .5
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . .6
PACKAGE THERMAL CHARACTERISTICS . . . . . . . .6
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . .6
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PIN CONFIGURATION-AD9891 . . . . . . . . . . . . . . . . . . .7
PIN FUNCTION DESCRIPTIONS-AD9891 . . . . . . . . . . .7
PIN CONFIGURATION-AD9895 . . . . . . . . . . . . . . . . . . .8
PIN FUNCTION DESCRIPTIONS-AD9895 . . . . . . . . . . .8
SPECIFICATION DEFINITIONS . . . . . . . . . . . . . . . . . . .9
EQUIVALENT CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . .9
TYPICAL PERFORMANCE CHARACTERISTICS . . . .10
SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Typical System Block Diagram . . . . . . . . . . . . . . . . . . . .11
PRECISION TIMING HIGH SPEED TIMING
GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Timing Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
High Speed Clock Programmability . . . . . . . . . . . . . . . . . .12
H-Driver and RG Outputs . . . . . . . . . . . . . . . . . . . . . . . . .13
Digital Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
HORIZONTAL CLAMPING AND BLANKING . . . . . . . .15
Individual CLPOB, CLPDM, and PBLK Sequences . . . . .15
Individual HBLK Sequences . . . . . . . . . . . . . . . . . . . . . . .15
Horizontal Sequence Control . . . . . . . . . . . . . . . . . . . . . . .15
VERTICAL TIMING GENERATION . . . . . . . . . . . . . . . .17
Individual Vertical Sequences . . . . . . . . . . . . . . . . . . . . . .18
Individual Vertical Regions . . . . . . . . . . . . . . . . . . . . . . . .19
Complete Field: Combining the Regions . . . . . . . . . . . . . .20
Vertical Sequence Alteration . . . . . . . . . . . . . . . . . . . . . . .21
Second Vertical Sequence During VSG Lines . . . . . . . . . .22
Vertical Sweep Mode Operation . . . . . . . . . . . . . . . . . . . .22
Vertical Multiplier Mode . . . . . . . . . . . . . . . . . . . . . . . . . .24
Frame Transfer CCD Mode . . . . . . . . . . . . . . . . . . . . . . 24
Vertical Sensor Gate (Shift Gate) Timing . . . . . . . . . . . . .25
SHUTTER TIMING CONTROL . . . . . . . . . . . . . . . . . . . .26
Normal Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
High Precision Shutter Mode . . . . . . . . . . . . . . . . . . . . . . .26
Low Speed Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . .26
SUBCK Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Readout After Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . .27
VSUB Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MSHUT and STROBE Control . . . . . . . . . . . . . . . . . . . .27
Example of Exposure and Readout of Interlaced Frame . . .29
ANALOG FRONT END DESCRIPTION AND
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Correlated Double Sampler . . . . . . . . . . . . . . . . . . . . . . . 30
Input Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PxGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PxGA Color Steering Mode Timing . . . . . . . . . . . . . . . . 31
Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PxGA and VGA Gain Curves . . . . . . . . . . . . . . . . . . . . .33
Optical Black Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
POWER-UP AND SYNCHRONIZATION . . . . . . . . . . . .34
Recommended Power-Up Sequence for Master Mode . . . .34
SYNC During Master Mode Operation . . . . . . . . . . . . . . .35
Synchronization in Slave Mode . . . . . . . . . . . . . . . . . . . . .35
POWER-DOWN MODE OPERATION . . . . . . . . . . . . . . 35
HORIZONTAL TIMING SEQUENCE EXAMPLE . . . . . 37
VERTICAL TIMING EXAMPLE . . . . . . . . . . . . . . . . . . . 39
CIRCUIT LAYOUT INFORMATION . . . . . . . . . . . . . . . .40
SERIAL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . .41
Notes About Accessing a Double-Wide Register . . . . . . . 41
NOTES ON REGISTER LISTING . . . . . . . . . . . . . . . . . . 42
COMPLETE REGISTER LISTING . . . . . . . . . . . . . . . . . 43
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 57
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
AD9891/AD9895–SPECIFICATIONSPOWER SUPPLY VOLTAGEThe total power dissipated by the HVDD supply may be approximated using the equation:
Total HVDD Power = [CLOAD � HVDD � Pixel Frequency] � HVDD � Number of H-Outputs Used
Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation.
Actual HVDD power may be slightly higher than the calculated value because of stray capacitance inherent in the PCB layout/routing.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONSLOGIC OUTPUTS (Except H and RG)
RG and H-DRIVER OUTPUTS (H1–H4)
Specifications subject to change without notice.
(RGVDD = HVDD = 4.75 V to 5.25 V, DVDD = DRVDD = 2.7 V to 3.5 V, CL = 20 pF, TMIN to TMAX,
unless otherwise noted.)
AD9891/AD9895
AD9891–ANALOG SPECIFICATIONSPIXEL GAIN AMPLIFIER (PxGA)
VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
A/D CONVERTERInput signal characteristics defined as follows:
1V MAX
INPUT
SIGNAL RANGE
200mV MAX
OPTICAL
BLACK PIXEL
500mV TYP
RESET
TRANSIENT
(AVDD1, AVDD2 = 3.0 V, fCLI = 20 MHz, TMIN to TMAX, unless otherwise noted.)
AD9891/AD9895
AD9895–ANALOG SPECIFICATIONSPIXEL GAIN AMPLIFIER (PxGA)
VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
A/D CONVERTERInput signal characteristics defined as follows:
1V MAX
INPUT
SIGNAL RANGE
200mV MAX
OPTICAL
BLACK PIXEL
500mV TYP
RESET
TRANSIENT
(AVDD1, AVDD2 = 3.0 V, fCLI = 30 MHz, TMIN to TMAX, unless otherwise noted.)
AD9891/AD9895
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9891 and AD9895 feature proprietary ESD protection circuitry, permanent damage may occur on
ABSOLUTE MAXIMUM RATINGSTCVDD
HVDD
RGVDD
DVDD
DRVDD
RG Output
H1–H4 Output
ORDERING GUIDE
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance�JA = 61°C/W
�JC = 29.7°C/W
TIMING SPECIFICATIONSAFE CLAMP PULSES
SERIAL INTERFACE (Figures 52 and 53)
NOTESParameter is programmable.Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
(CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 20 MHz [AD9891] or 30 MHz [AD9895], unless
otherwise noted.)
AD9891 PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS1NOTESSee Figure 50 for circuit configuration.AI = Analog Input, AO = Analog Output, DI = Digital Input,
AD9891/AD9895
AD9895 PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS1NOTESSee Figure 50 for circuit configuration.AI = Analog Input, AO = Analog Output, DI = Digital Input,
SPECIFICATION DEFINITIONS
Differential Nonlinearity (DNL)An ideal ADC exhibits code transitions that are exactly 1LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096codes, respectively,
must be present over all operating conditions.
Peak NonlinearityPeak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9891/AD9895 from a
true straight line. The point used as “zero scale” occurs 0.5 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 and 0.5LSB beyond the last code transition. The
deviation is measured from the middle of each particular output
code to the true straight line. The error is then expressed as a
EQUIVALENT CIRCUITSpercentage of the 2V ADC full-scale signal. The input signal is
always appropriately gained up to fill the ADC’s full-scale range.
Total Output NoiseThe rms output noise is measured using histogram techniques. The
standard deviation of the ADC output codes is calculated in LSB
and represents the rms noise level of the total signal chain at the
specified gain setting. The output noise can be converted to an
equivalent voltage, using the relationship 1LSB= (ADC Full
Scale/2n codes) when n is the bit resolution of the ADC. For the
AD9891, 1LSB is 2mV, while for the AD9895, 1 LSB is 0.5 mV.
Power Supply Rejection (PSR)The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
HVDD OR
RGVDD
HVSS OR
RGVSS
OUTPUT
RG, H1–H4
ENABLEFigure 4.H1–H4, RG Drivers
Figure 1.CCDIN
DVDD
DVSSDRVSS
DRVDD
THREE-
STATE
DATA
DOUTFigure 2.Digital Data Outputs
Figure 3.Digital Inputs
AD9891/AD9895–Typical Performance CharacteristicsTPC 1.AD9891 Power vs. Sample Rate
TPC 2.AD9891 Typical DNL Performance
TPC 3.AD9891 Output Noise vs. VGA Gain
TPC 4. AD9895 Power vs. Sample Rate
TPC 5. AD9895 Typical DNL Performance
TPC 6. AD9895 Output Noise vs. VGA Gain
SYSTEM OVERVIEWFigure 5 shows the typical system block diagram for the AD9891/
AD9895 used in Master Mode. The CCD output is processed by
the AD9891/AD9895’s AFE circuitry, which consists of a CDS,
PxGA, VGA, black level clamp, and an A/D converter. The digi-
tized pixel information is sent to the digital image processor chip,
which performs the post-processing and compression. To operate
the CCD, all CCD timing parameters are programmed into the
AD9891/AD9895 from the system microprocessor, through the
3-wire serial interface. From the system master clock, CLI, pro-
vided by the image processor or external crystal, the AD9891/
AD9895 generates all of the CCD’s horizontal and vertical clocks
and all internal AFE clocks. External synchronization is provided
by a SYNC pulse from the microprocessor, which will reset
internal counters and resync the VD and HD outputs.
Figure 5.Typical System Block Diagram, Master Mode
Alternatively, the AD9891/AD9895 may be operated in Slave
Mode, in which the VD and HD are provided externally from
the image processor. In this mode, all AD9891/AD9895 timing
will be synchronized with VD and HD.
The H-drivers for H1–H4 and RG are included in the AD9891/
AD9895, allowing these clocks to be directly connected to the CCD.
H-drive voltage of up to 5V is supported. An external V-driver is
required for the vertical transfer clocks, the sensor gate pulses,
and the substrate clock.
The AD9891/AD9895 also includes programmable MSHUT
and STROBE outputs, which may be used to trigger mechani-
cal shutter and strobe (flash) circuitry.
Figure 6 shows the horizontal and vertical counter dimensions
for the AD9891/AD9895. All internal horizontal and vertical
clocking is programmed using these dimensions to specify line
and pixel locations.
Figure 6.Vertical and Horizontal Counters
AD9891/AD9895
PRECISION TIMING HIGH SPEED TIMING GENERATIONThe AD9891/AD9895 generates flexible, high speed timing
signals using the Precision Timing core. This core is the founda-
tion for generating the timing used for both the CCD and the
AFE: the reset gate RG, horizontal drivers H1–H4, and the
SHP/SHD sample clocks. A unique architecture makes it rou-
tine for the system designer to optimize image quality by
providing precise control over the horizontal CCD readout and
the AFE correlated double sampling.
The high speed timing of the AD9891/AD9895 operates the
same in either Master or Slave Mode configuration.
Timing ResolutionThe Precision Timing core uses a 1� master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel
clock frequency. Figure7 illustrates how the internal timing
core divides the master clock period into 48steps or edge posi-
tions. Using a 20MHz CLI frequency, the edge resolution of
the Precision Timing core is 1ns. If a 1� system clock is not
available, it is also possible to use a 2� reference clock by pro-
gramming the CLIDIVIDE Register (Addr x01F). The AD9891/
AD9895 will then internally divide the CLI frequency by two.
The AD9891/AD9895 also includes a master clock output,
CLO, which is the inverse of CLI. This output is intended to be
used as a crystal driver. A crystal can be placed between the
CLI and CLO Pins to generate the master clock for the
AD9891/AD9895. For more information on using a crystal, see
Figure 51.
High Speed Clock ProgrammabilityFigure 8 shows how the high speed clocks RG, H1–H4, SHP,
and SHD are generated. The RG pulse has programmable
rising and falling edges, and may be inverted using the polarity
control. The horizontal clocks H1 and H3 have programmable
rising and falling edges and polarity control. The H2 and H4
clocks are always inverses of H1 and H3, respectively.
TableI summarizes the high speed timing registers and their
parameters. Figure9 shows the typical 2-phase H-clock
arrangement in which H3 and H4 are programmed for the same
edge location as H1 and H2.
The edge location registers are sixbits wide, but there are only
48 valid edge locations available. Therefore, the register values
are mapped into four quadrants, with each quadrant containing
12 edge locations. Table II shows the correct register values for
Figure 7.High Speed Clock Resolution from CLI Master Clock Input
the corresponding edge locations. Figure 10 shows the range
and default locations of the high speed clock signals.
H-Driver and RG OutputsIn addition to the programmable timing positions, the AD9891/
AD9895 features on-chip output drivers for the RG and H1–H4
outputs. These drivers are powerful enough to directly drive the
CCD inputs. The H-driver current can be adjusted for optimum
rise/fall time into a particular load by using the DRV Registers
(Addr x0E1to x0E4). The RG drive current is adjustable using
the RGDRV Register (Addr x0E8). Each 3-bit DRV Register is
adjustable in 3.5mA increments, with the minimum setting of 0
equal to OFF or three-state, and the maximum setting of 7
equal to 24.5mA.
As shown in Figure 11, the H2 and H4 outputs are inverses of
H1 and H3, respectively. The internal propagation delay resulting
from the signal inversion is less than 1 ns, which is significantly
less than the typical rise time driving the CCD load. This results
in an H1/H2 crossover voltage at approximately 50% of the out-
put swing. The crossover voltage is not programmable.
Digital Data OutputsThe AD9891/AD9895 data output and DCLK phase are pro-
grammable using the DOUTPHASE Register (Addr x01D). Any
edge from 0 to 47 may be programmed, as shown in Figure12.
Normally, the DOUT and DCLK signals will track in phase,
based on the DOUTPHASE Register contents. The DCLK
output phase can also be held fixed with respect to the data
outputs, by changing the DCLKMODE Register (Addr x01E)
HIGH. In this mode, the DCLK output will remain at a fixed
phase equal to CLO (the inverse of CLI) while the data output
phase is still programmable.
There is a fixed output delay from the DCLK rising edge to the
DOUT transition, called tOD. This delay can be programmed to
four values between 0ns and 12ns, using the DOUT_DELAY
Register (Addr x032). The default value is 8ns.
Table I.H1–H4, RG, SHP, and SHD Timing ParametersFigure 9.2-Phase H-Clock Operation
Table II.Precision Timing Edge Locations
AD9891/AD9895Figure 10.High Speed Clock Default and Programmable Locations
Figure 11.H-Clock Inverse Phase Relationship
Figure 12.Digital Output Phase Adjustment
HORIZONTAL CLAMPING AND BLANKINGThe AD9891/AD9895’s horizontal clamping and blanking pulses
are fully programmable to suit a variety of applications. As with
the vertical timing generation, individual sequences are defined
for each signal, which are then organized into multiple regions
during image readout. This allows the dark pixel clamping and
blanking patterns to be changed at each stage of the readout in
order to accommodate different image transfer timing and high
speed line shifts.
Individual CLPOB, CLPDM, and PBLK SequencesThe AFE horizontal timing consists of CLPOB, CLPDM, and
PBLK, as shown in Figure13. These three signals are indepen-
dently programmed using the registers in Table III. SPOL is
the start polarity for the signal, and TOG1 and TOG2 are the
first and second toggle positions of the pulse. All three signals
are active low and should be programmed accordingly. Up to
four individual sequences can be created for each signal.
To simplify the programming requirements, the CLPDM signal
will track the CLPOB signal by default. If separate control of
the CLPDM signal is desired, the SINGLE_CLAMP Register
(Addr x031) should be set LOW.
Individual HBLK SequencesThe HBLK programmable timing shown in Figure14 is similar
to CLPOB, CLPDM, and PBLK. However, there is no start
polarity control. Only the toggle positions are used to designate
the start and the stop positions of the blanking period. Addition-
ally, there is a polarity control, HBLKMASK, that designates the
polarity of the horizontal clock signals H1–H4 during the blank-
ing period. Setting HBLKMASK high will set H1= H3= Low
and H2= H4= High during the blanking, as shown in Figure15.
Up to four individual sequences are available for HBLK.
Horizontal Sequence ControlThe AD9891/AD9895 use sequence change positions (SCP)
and sequence pointers (SPTR) to organize the individual hori-
Figure 13.Clamp and Preblank Pulse Placement
Figure 14.Horizontal Blanking (HBLK) Pulse Placement
AD9891/AD9895
Table III.CLPOB, CLPDM, and PBLK Individual Sequence Parameters
Table IV.HBLK Individual Sequence Parameters
Table V.Horizontal Sequence Control Parameters for CLPOB, CLPDM, and PBLK
Table VI.Horizontal Sequence Control Parameters for HBLKVTPRCP7
HBLKSPTR0–
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE PROGRAMMED WITH-
IN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
SEQUENCE CHANGE POSITION #1
SEQUENCE CHANGE POSITION #2
SEQUENCE CHANGE POSITION #3
SINGLE FIELD (1 VD INTERVAL)
SEQUENCE CHANGE POSITION #0
(V-COUNTER = 0)Figure 16.Clamp and Blanking Sequence Flexibility
zontal sequences. Up to four SCPs are available to divide the
readout into four separate regions, as shown in Figure16. The
SCP0 is always hard-coded to line 0, and SCP1–SCP3 are
register programmable. During each region bound by the SCP,
the SPTR Registers designate which sequence is used by each
signal. CLPOB and CLPDM share the same SCP, PBLK has a
separate set of SCP, and HBLK shares the vertical RCP (see
Vertical Timing Generation section). For example,
CLPSCP1 will define Region 0 for CLPOB and CLPDM,
and in that region any of the four individual CLPOB and
CLPDM sequences may be selected with the SPTR Registers.
The next SCP defines a new region, and in that region each
signal can be assigned to a different individual sequence. Be-
cause HBLK shares the vertical RCP, there are up to eight
regions where HBLK sequences may be changed using the eight
HBLKSPTR Registers.
VERTICAL TIMING GENERATIONThe AD9891/AD9895 provide a very flexible solution for gener-
ating vertical CCD timing and can support multiple CCDs and
different system architectures. The 4-phase vertical transfer
clocks V1–V4 are used to shift each line of pixels into the hori-
zontal output register of the CCD. The AD9891/AD9895 allow
these outputs to be individually programmed into different pulse
patterns. Vertical sequence control registers then organize the
individual vertical pulses into the desired CCD vertical timing
arrangement.
Figure17 shows an overview of how the vertical timing is gener-
ated in three basic steps. First, the individual pulse patterns or
sequences are created by using the Vertical Transfer Pulse (VTP)
Registers. These sequences are a essentially a “pool” of pulse
patterns that may be assigned to any of the V1-V4 outputs. Sec-
ond, individual regions are built by assigning a sequence to each
of the V1–V4 outputs. Up to five unique regions may be speci-
fied. Finally, the readout of the entire field is constructed by
combining one or more of the individual regions sequentially.
With up to eight region areas available, different steps of the
readout such as high speed line shifts and vertical image transfer
can be supported.
Figure 17.Summary of Vertical Timing Generation
AD9891/AD9895
Individual Vertical SequencesTo generate the individual vertical sequences or patterns shown
in Figure 18, five registers are required for each sequence.
Table VII summarizes these registers and their respective bit
lengths. The start polarity (VTPPOL) determines the starting
polarity of the vertical sequence and can be programmed high
or low. The first toggle position (VTPTOG1) and second
toggle position (VTPTOG2) are the pixel locations within the line
where the pulse transitions. A third toggle position
(VTPTOG3) is also available for sequences 0 through 7. All
toggle positions are 10-bit values, which limits the placement of
a pulse to within 1024 pixels of a line. A separate register,
VSTART, sets the start position of the sequence within the line
(see Individual Vertical Regions section). The Length
(VTPLEN) Register determines the number of pixels between
each of the pulse repetitions, if any repetitions have been
programmed. The number of repetitions (VTPREP) simply
determines the number of pulse repetitions desired within a
single line. Programming “1” for VTPREP gives a single
pulse, while setting to “0” will provide a fixed dc output based
on the start polarity value. There is a total of 12 individual
sequences that may be programmed.
When specifying the individual regions, each sequence may be
assigned to any of the V1–V4 outputs. For example, Figure 19
shows a typical 4-phase V-clock arrangement. Two different
sequences are needed to generate the different pulsewidths.
The use of individual start positions for V1–V4 allows the four
outputs to be generated from two sequences. Figure 20 shows a
slightly different V-clock arrangement in which V2, V3, and V4
are simply shifted and/or inverted versions of V1. Only one
individual sequence is needed because all signals have the same
pulsewidth. The invert sequence registers (VINV) are used for
V3 and V4 (see Table VII).
Note that for added flexibility, the VTPPOL Registers (Start
Polarity) may be used as an extra toggle position.
Table VII.Individual VTP Sequence ParametersFigure 18. Individual Vertical Sequence Programmability
Individual Vertical RegionsThe AD9891/AD9895 arranges the individual sequences into re-
gions through the use of Sequence Pointers (SPTR). Within each
region, different sequences may be assigned to each V-clock
output. Figure21 shows the programmability of each region
and TableVIII summarizes the registers needed for generating
each region.
For each individual region, the line length (in pixels) is programmable
using the HDLEN Registers. Each region can have a different
line length to accommodate various image readout techniques.
The maximum number of pixels per line is 4096. Also unique to
each region are the sequence start positions for each V-output,
which are programmed using the VSTART Registers. Each
VSTART is a 12-bit value, allowing the start position to be
placed anywhere in the line. There are five HDLEN Registers,
one for each region. There is a total of 20 VSTART Registers:
one for each V1–V4 output, for five different regions.
Note that the last line of the field is separately programmable
using the HDLASTLEN Register.
The Sequence Pointer registers VxSPTRFIRST and
VxSPTRSECOND assign the individual vertical sequences to
each of the V-clock outputs (V1–V4) within a given region.
Typically, only the SPTRFIRST Registers are used, with the
SPTRSECOND Registers reserved for generating line-by-line
alternation (see Vertical Sequence Alternation). Any of the 12
individual sequences may also be inverted using the
VxINVFIRST and VxINVSECOND Registers, effectively dou-
bling the number of sequences available. There is one
SPTRFIRST Register for each V-output, for a total of four regis-
ters per region. If all five regions are used, there is a total of 20
SPTRFIRST Registers. There is also the same number of
SPTRSECOND Registers, if alternation is required. Note that the
SPTR Registers are fourbits wide; if a value greater than 11 is
programmed, the Vx output will be dc at the level of the
VxINV Register.
Figure 20.Example of Inverted V1–V4 Signals Using One Individual Sequence with Inversion
Figure 21.Individual Vertical Region Programmability
AD9891/AD9895
Complete Field: Combining the RegionsThe individual regions are combined into a complete field readout
by using region change positions (RCP) and region pointers
(REGPTR). Figure22 shows how each field is divided into
multiple regions. This allows the user to change the vertical
timing during various stages of the image readout. The boundaries
of each region are defined by the sequence change positions
(RCP). Each RCP is a 12-bit value representing the line number
bounding the region. A total of seven RCPs allow up to eight
different region areas in the field to be defined. The first RCP is
always hard-coded to zero, and the remaining seven are register
programmable. Note that there are only five possible individual
regions that can be defined, but the eight region areas allow the
same region to be used in more than one place during the field.
Within each region area, the region pointers specify which of the
five individual regions will be used. There are eight region
pointers, one for each region area. Table IX summarizes the
registers for the region change positions and region pointers.
Figure 22.Complete Field Using Multiple Region Areas
Table VIII.Individual Vertical Region ParametersVxSTART
VxSPTRFIRST
x is the V-output from 1–4.
Table IX.Complete Vertical Field Registers
Table X.Vertical Sequence Alternation Parametersx is the V-output from 1–4.
Vertical Sequence AlternationThe AD9891/AD9895 also supports line-by-line alternation of
vertical sequences within any region, as shown in Figure23.
TableX summarizes the additional registers used to support differ-
ent alternation patterns. To create an alternating vertical pattern,
the VxSPTRFIRST and VxSPTRSECOND Registers are pro-
grammed with the desired sequences to be alternated. The
VTPALT Register must be set HIGH for that region to use
alternation. If VTPALT is LOW, then the VxSPTRSECOND
Registers will be ignored. Figure24 shows an example of line-
by-line alternation.
REGION CHANGE POSTION #2
SINGLE FIELD (1 VD INTERVAL)
SECOND LINES
FIRST LINES
LINE-BY-LINE ALTERNATION
NO ALTERNATION
REGION CHANGE POSITION #1
ONLY FIRST LINES ARE USED
REGION CHANGE POSTION #0
NO ALTERNATIONONLY FIRST LINES ARE USED
WHEN THE VTPALT REGISTER IS LOW (NO ALTERNATION), ONLY THE FIRST LINES ARE USED. Figure 23.Use of Line Alteration in Vertical Sequencing
Figure 24.Example of Line Alteration within a Region
AD9891/AD9895
Second Vertical Sequence During VSG LinesMost CCDs require additional vertical timing during the sensor
gate line. The AD9891/AD9895 supports the option to output a
second set of sequences for V1–V4 during the line when the sen-
sor gates VSG1–VSG4 are active. Figure25 shows a typical VSG
line, which includes two separate sets of vertical sequences on V1–
V4. The sequences at the start of the line are the same as those
generated in the previous line. But the second sequence only
occurs in the line where the VSG signals are active. To select the
sequences used for the second sequence, the registers in
TableXI are used. To enable the second set of sequences during
the VSG line, the VTP_SGLINEMODE is set HIGH. As with
the standard vertical regions, each V1–V4 output has an indi-
vidual start position, programmed in the VxSTART_SGLINE
Registers. Each V1–V4 output can select from the pool of 12
unique sequences using individual sequence pointer registers,
VxSPTR_SGLINE. Also, any sequence may be inverted for a
particular V1–V4 output by using the VxINV_SGLINE Registers.
Vertical Sweep Mode OperationThe AD9891/AD9895 contains a special mode of vertical timing
operation called Sweep Mode. This mode is used to generate a
large number of repetitive pulses that span across multiple HD
lines. One example of where this mode may be needed is at the
start of the CCD readout operation. At the end of the image
exposure, but before the image is transferred by the sensor gate
pulses, the vertical interline CCD Registers should be “clean” of
all charge. This can be accomplished by quickly shifting out any
charge with a long series of pulses on the V1–V4 outputs. De-
pending on the vertical resolution of the CCD, up to two or
three thousand clock cycles will be needed to shift the charge out
of each vertical CCD line. This operation will span across mul-
tiple HD line lengths. Normally, the AD9891/AD9895 sequences
are contained within one HD line length. But when Sweep Mode
is enabled, the HD boundaries will be ignored until the region is
finished. To enable Sweep Mode within any region, program
the appropriate SWEEP (0–4) Registers to HIGH.
Figure26 shows an example of the Sweep Mode operation. The
number of vertical pulses needed will depend on the vertical
resolution of the CCD. The V1–V4 output signals are generated
using the Individual Vertical Sequence Registers (shown in Table
VII). A single pulse is created using the first, second, and third
toggle positions, and then the number of repeats is set to the
number of vertical shifts required by the CCD. The maximum
number of repeats is 4096 in this mode, using the VTPREP
Register. This produces a pulse train of the appropriate length.
Normally, the pulse train would be truncated at the end of the
HD line length. But with Sweep Mode enabled for this region, the
HD boundaries will be ignored. In Figure26, the sweep region
occupies 23 HD lines. After the Sweep Mode region is completed,
normal sequence operation will resume in the next region.
Table XI.Second Vertical Sequence Registers During SG Linesx is the V-output from 1–4.
Figure 25.Example of Second Sequences During Sensor Gate Line
Figure 26.Example of Sweep Region for High Speed Vertical Shift
AD9891/AD9895
Vertical Multiplier ModeTo generate very wide vertical timing pulses, a vertical region may
be configured into Multiplier Mode. This mode uses the vertical
sequence registers in a slightly different manner. Multiplier Mode
can be used to support unusual CCD timing requirements, such as
vertical pulses that are wider than a single HD line length.
The start polarity and toggle positions are still used in the same
manner as the standard sequence generation, but the length is
used differently. Instead of using the pixel counter (HD counter)
to specify the toggle position locations (VTPTOG1, 2, 3) of the
sequence, VTP length (VTPLEN) is multiplied by the
VTPTOG position to allow very long sequences to be generated.
To calculate the exact toggle position, counted in pixels after the
start position:
Because the VTPTOG Register is multiplied by VTPLEN, the
resolution of the toggle position placement is reduced. If
VTPLEN= 4, the toggle position accuracy is now reduced to
4-pixel steps instead of single pixel steps. TableXII summarizes
how the Individual Vertical Sequence Registers are pro-
grammed for Multiplier Mode operation. Note that the bit
ranges for the VTPTOG and VTPREP Registers differ from the
normal operation shown in TableVII. In Multiplier Mode, the
VTPREP Register should always be programmed to the same
value as the highest toggle position register.
The example shown in Figure27 illustrates this operation. The
first toggle position is 2 and the second toggle position is 9. In
Nonmultiplier Mode, this would cause the V-sequence to
toggle at pixel 2 and then pixel 9 within a single HD line. How-
ever, now toggle positions are multiplied by the VTPLEN= 4,
so the first toggle occurs at pixel count= 8, and the second toggle
occurs at pixel count= 36. Sweep Mode should be enabled to
allow the toggle positions to cross the HD line boundaries.
Frame Transfer CCD ModeThe AD9891/AD9895 may also be configured for use with frame
transfer CCDs. In Frame Transfer CCD (FTCCD) Mode,
an additional four vertical outputs are available for a total of
eight outputs (V1–V8). In this case, V1–V4 are used for clock-
ing the active image area, and V5–V8 are used for clocking the
storage area. In FTCCD Mode, the sequences assigned to the
V1–V4 outputs are duplicated at the V5–V8 outputs to allow the
storage area to be clocked along with the image area. Individual
masking of the V1–V4 and V5–V8 outputs allows for vertical
decimation techniques during transfer from the image to the
storage area. The additional outputs V5–V8 are available on four
of the sensor gate output pins, VSG1–VSG4. Figure28 shows
an example of the eight V-clocks configured for use with a frame
transfer CCD.
Figure 27.Example of Multiplier Region for Wide Vertical Pulse Timing
Table XII.Multiplier Mode and Sequence Register Parameters
Figure 28.Example of Frame Transfer CCD Mode using V1–V8
The frame transfer CCD also requires additional timing control
when decimating the image for Preview Mode. The
AD9891/AD9895 contain registers to independently stop the
operation of the V5–V8 outputs while the V1–V4 outputs con-
tinue to run or to stop the V1–V4 outputs, while the V5–V8
outputs remain operational. The FREEZE and RESUME Regis-
ters specify the pixel locations within each line of a region where
the V1–V4 or V5–V8 clock outputs will start to hold their state,
and where they will resume normal operation. FREEZE and
RESUME can be used in any region during the frame readout.
Vertical Sensor Gate (Shift Gate) TimingWith an interline CCD, the vertical sensor gates (VSG) are used to
transfer the pixel charges from the light-sensitive image area into the
light-shielded vertical registers. When a mechanical shutter is not being
used, this transfer will effectively end the exposure period during the
image acquisition. From the light-shield vertical registers, the image
is then read out line-by-line by using the vertical transfer pulses
V1–V4 in conjunction with the high speed horizontal clocks.
Figure 29.Vertical Sensor Gate Pulse Placement
Table XIII.Sensor Gate Register Parameters
AD9891/AD9895TableXIII contains the summary of the VSG Registers. The
AD9891/AD9895 has eight SG outputs, VSG1–VSG8. Each of
the outputs can be assigned to one of four programmed
sequences by using the SGSEL1–SGSEL8 Registers. Each
sequence is generated in the same manner as the individual vertical
sequences, with a programmable start polarity (SGPOL), first toggle
position (SGTOG1), and second toggle position (SGTOG2).
The active line where the VSG1–VSG8 pulses occur is program-
mable using the two SGACTLIN Registers. Additionally, any
of the VSG1–VSG8 pulses may be individually disabled by
using the SGMASK Register. The masking allows all of the differ-
ent SG sequences to be preprogrammed and the appropriate
pulses for odd or even fields can be masked.
SHUTTER TIMING CONTROLCCD image exposure time is controlled through use of the substrate
clock signal (SUBCK), which pulses the CCD substrate to clear
out accumulated charge. The AD9891/AD9895 supports three
types of electronic shuttering: Normal Shutter Mode, High Preci-
sion Shutter Mode, and Low Speed Shutter Mode. Along with the
SUBCK pulse placement, the AD9891/AD9895 can accommo-
date different progressive and interlaced readout modes.
Additionally, the AD9891/AD9895 provides output signals to
control an external mechanical shutter, strobe (flash), and the
CCD bias for still mode readout (VSUB).
Normal Shutter ModeFigure 30 shows the VD and SUBCK output for Normal Shut-
ter Mode. The SUBCK will pulse once per line, and the total
number of repetitions within the field is programmable. The
pulse polarity, width, and line location is programmable using
the SUBCKPOL, SUBCK1TOG1, and SUBCK1TOG2 Regis-
ters (see Table XIV). The number of SUBCK pulses per field is
programmed in the SUBCKNUM Register.
As shown in Figure 30, the SUBCK pulses will always begin
on the line after the sensor gates occur, specified by the
SGACTLINE Register (Addr x265 and Addr x266). The
SUBCKPOL, SUBCK1TOG, SUBCK2TOG, and
SUBCKNUM Registers are updated at the start of the line after
the sensor gate line. All other shutter mode registers are up-
dated with the majority of the AD9891/AD9895’s registers at
the VD/HD falling edge.
High Precision Shutter ModeHigh precision shuttering is controlled in the same way as nor-
mal shuttering but requires a second set of toggle registers. In
this mode, the SUBCK still pulses once per line, but the last
SUBCK in the field will have an additional SUBCK pulse
whose location is determined by the SUBCK2TOG1 and
SUBCK2TOG2 Registers (see Figure 31). Finer resolution of
the exposure time is possible using this mode. Leaving both
SUBCK2TOG Registers set to 4095 (x3F) will disable the High
Precision Mode (default setting).
Low Speed Shutter ModeFor normal exposure times less than one field interval, the
EXPOSURE Register will be set to 0. Exposure times greater
than one field interval can be achieved by writing a value
greater than zero to the EXPOSURE Register. As shown in
Figure 32, this shutter mode will suppress the SUBCK and
VSG outputs for up to 4095 fields (VD periods). The VD and
HD outputs may be suppressed during the exposure period by
programming the VDHDOFF Register to 1.
Figure 30.Normal Shutter Mode
SUBCK SuppressionNormally, the SUBCKs will begin to pulse on the line following
the sensor gate line (VSG). With some CCDs, the SUBCKs
need to be suppressed for one or more lines following the VSG
line. The SUBCKSUPPRESS Register allows for the suppression
the SUBCK pulses for up to 63 lines following the VSG line.
Readout After ExposureA write to the EXPOSURE Register will designate the number
fields in the exposure time (tEXP) from 0to 4095. After the exposure,
the readout of the CCD data occurs. During readout, the
SUBCK output may need to be further suppressed until the
readout is completed. The READOUT Register specifies the
number of additional fields after the exposure to continue the
suppression of SUBCK. READOUT can be programmed for
zero to seven additional fields and should be preprogrammed at
start-up, not at the same time as the exposure write. A typical
interlaced CCD frame readout mode will generally require two
additional fields of SUBCK suppression (READOUT = 2).
Note that a write to the EXPOSURE Register acts as a trigger
for readout after the exposure is completed. If no write to the
EXPOSURE Register occurs, than the READOUT Register will
have no effect. See Figure35 for an example of triggering the
exposure and subsequent readout.
VSUB ControlThe CCD readout bias (VSUB) can be programmed to accom-
modate different CCDs. Figure35 shows two different modes
that are available. In Mode 0, VSUB goes active during the
field of the last SUBCK when the exposure begins. The
on-position (rising edge in Figure35) is programmable to any
line within the field. VSUB will remain active until the end of
the image readout. In Mode 1, the VSUB is not activated
until the start of the readout.
MSHUT and STROBE ControlMSHUT and STROBE operation is shown in Figures33, 34,
and 35. Table XV shows the registers parameters for control-
ling the MSHUT and STROBE outputs. The MSHUT output
is switched on with the MSHUTON Registers, and it will
remain on until the location specified in the MSHUTOFF
Registers. The location of MSHUTOFF is fully programmable to
anywhere within the exposure period, using the FD (field), LN
(line), and PX (pixel) Registers. The STROBE pulse is defined
by the ON and OFF positions. STROBON_FD is the field in
which the STROBE is turned on, measured from the field con-
taining the last SUBCK before exposure begins. The
STROBON_ LN and STROBON_PX Registers give the line
and pixel positions with respect to STROBON_FD. The
STROBE off position is programmable to any field, line, and
pixel location with respect to the field of the last SUBCK.
Figure 32.Low Speed Shutter Mode Using EXPOSURE Register
Table XIV.Electronic Shutter Mode Register ParametersSUBCK1TOG1*
SUBCK1TOG2*
SUBCK2TOG1*
SUBCK2TOG2*
SUBCKNUM*
SUBCKSUPPRESS*
EXPOSURE
AD9891/AD9895Figure 33.MSHUT Output Programmability
Figure 34.STROBE Output Programmability
Table XV.VSUB, MSHUT, and STROBE Register Parameters
Figure 35.Exposure and Readout of Interlaced Frame
Example of Exposure and Readout of Interlaced FrameFigure35 shows the sequence of events for a typical exposure and
readout operation using a mechanical shutter and strobe. The
register values for the VSUB, MSHUT, and STROBE toggle
positions may be previously loaded at any time, prior to triggering
these functions. Additional register writes are required to configure
the vertical clock outputs, V1–V4, which are not described here.Write to the READOUT Register (Addr x281) to specify
the number of fields to further suppress SUBCK while the
CCD data is readout. In this example, READOUT= 2.Write to the EXPOSURE Register (Addr x27D) to start the
exposure and specify the number of fields to suppress
SUBCK and VSG outputs during exposure. In this example,
EXPOSURE= 2.
Write to the TRIGGER Register (Addr x280) to enable the
STROBE, MSHUT, and VSUB signals. To trigger all three
signals (as in Figure36) the register TRIGGER= 7.
Write to the SGACTLINE Register (Addr x265 and
Addr x266) and SGMASK Register (Addr x26F and
Addr x270) to configure the sensor gates for ODD field
readout (interlaced CCD).VD/HD falling edge will update the serial writes from 1.If VSUB Mode= 0, VSUB output turns ON at the line
specified in the VSUBON Register (Addr x272 and
Addr x273).
STROBE output turns ON at the location specified in the
STROBON Registers (Addr x294 to Addr x299).STROBE output turns OFF at the location specified in the
STROBEOFF Registers (Addr x29A to Addr x29F).MSHUT Output turns OFF at the location specified in the
MSHUTOFF Registers (Addr x28D to Addr x292).Write to the SGACTLINE Register (Addr x253 and
Addr x254) and SGMASK Register to configure the sensor
gates for EVEN field readout.VD/HD falling edge will update the serial writes from 6.Write to the SGACTLINE Register and SGMASK Register
to reconfigure the sensor gates for Draft/Preview Mode output.
Write to the MSHUTON Register (Addr x287) to reopen
the mechanical shutter for Draft/Preview Mode.VD/HD falling edge will update the serial writes from 8.
10:VSG outputs returns to Draft/Preview Mode timing.
SUBCK output resumes operation.
MSHUT output returns to the ON position (Active or
“Open”).
VSUB output returns to the OFF position (Inactive).
