AD9859YSV Fast Delivery |IC PHOENIX CO.,LIMITED

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AD9859YSV
400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer
400 MSPS, 10-Bit, 1.8 V CMOS
Direct Digital Synthesizer
Rev. 0
FEATURES
400 MSPS internal clock speed
Integrated 10-bit DAC
32-bit tuning word
Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)
Excellent dynamic performance
>75 dB SFDR @ 160 MHz (±100 kHz offset) AOUT
Serial I/O control
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP/EP package
Support for 5 V input levels on most digital inputs
PLL REFCLK multiplier (4× to 20×)
Internal oscillator; can be driven by a single crystal
Phase modulation capability
Multichip synchronization
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generators
Test and measurement equipment
Commercial and amateur radio exciter
GENERAL DESCRIPTION
The AD9859 is a direct digital synthesizer (DDS) featuring a
10-bit DAC operating at up to 400 MSPS. The AD9859 uses
advanced DDS technology, coupled with an internal high speed,
high performance DAC to form a digitally programmable,
complete high frequency synthesizer capable of generating a
frequency-agile analog output sinusoidal waveform at up to
200 MHz. The AD9859 is designed to provide fast frequency
hopping and fine tuning resolution (32-bit frequency tuning
word). The frequency tuning and control words are loaded into
the AD9859 via a serial I/O port.
The AD9859 is specified to operate over the extended industrial
temperature range of –40°C to +105°C
FUNCTIONAL BLOCK DIAGRAM
I/O UPDATE
DAC_RSET
IOUT
IOUT
OSK
PWRDWNCTL
REFCLK
REFCLK
CRYSTAL OUTI/O PORT
SYNC_IN
SYNC_CLK
RESET
Figure 1.
TABLE OF CONTENTS
AD9859—Electrical Specifications................................................3
Absolute Maximum Ratings............................................................5
Pin Configuration.............................................................................6
Pin Function Descriptions..............................................................7
Typical Performance Characteristics.............................................8
Theory of Operation......................................................................11
Component Blocks.....................................................................11
Modes of Operation...................................................................16
Programming AD9859 Features...............................................16
Serial Port Operation.................................................................19
Instruction Byte..........................................................................21
Serial Interface Port Pin Description.......................................21
MSB/LSB Transfers....................................................................21
Suggested Application Circuits.....................................................23
Outline Dimensions.......................................................................24
ESD Caution................................................................................24
Ordering Guide..........................................................................24
REVISION HISTORY
Revision 0: Initial Version
AD9859—ELECTRICAL SPECIFICATIONS
Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, RSET = 3.92 kΩ, External Reference Clock Frequency = 20
MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.
Table 1.

1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude reduces the phase noise perform-
ance of the device.
2 Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions of the AD9859 section). The longest time required is for the
reference clock multiplier PLL to relock to the reference. The wake-up time assumes that there is no capacitor on DACBP and that the recommended PLL loop filter
values are used. SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK fre-
quency is the same as the external reference clock frequency.
4 SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set. This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
IOUT
MUSTTERMINATEOUTPUTS TO AVDD. DONOT EXCEED THEOUTPUT VOLTAGECOMPLIANCE RATING.
DACOUTPUTS
DVDD_I/O
INPUT
DIGITALINPUTS
AVOIDOVERDRIVINGDIGITAL INPUTS.FORWARD BIASINGESD DIODES MAYCOUPLE DIGITAL NOISEONTO POWER PINS.03374-0-032
Figure 2. Equivalent Input and Output Circuits
PIN CONFIGURATION
I/O UPDATE
DVDD
DGND
AVDD
AGND
AVDD
AGND
OSC/REFCLK
OSC/REFCLK
CRYSTAL OUT
LOOP_FILTER
AGNDAV
AGNDAV
AGNDAV
IOUT
IOUT
DACBP
AGND
OSKDGNDDGND
NC_
DD_
I/O
DGNDSDIOSYN
RESET
PWRDWNCTL
DVDD
DGND
AGND
AGND
AGND
AVDD
AGND
AVDD
AGND
AVDD
03375-0-002DAC_
SET
Figure 3. 48-Lead TQFP/EP
Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to
analog ground. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or 3.3 V; however, the DVDD pins (Pin 2 and Pin 34) can only
be powered to 1.8 V.
PIN FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions—48-Lead TQFP/EP
TYPICAL PERFORMANCE CHARACTERISTICS
20dB
CENTER 100MHz–100
20MHz/SPAN 200MHz
REF LVL
–5dBm
10kHz
10kHz
RBW
VBW
SWT
RF ATT
UNIT
DELTA [T1]
–65.10dB
98.19639279MHz
Figure 4. FOUT = 1 MHz FCLK = 400 MSPS, WBSFDR
20dB
CENTER 100MHz
20MHz/SPAN 200MHz
REF LVL
–5dBm
10kHz
10kHz
RBW
VBW
SWT
RF ATT
UNIT
DELTA [T1]
–65.02dB
81.36272545MHz
Figure 5. FOUT = 10 MHz, FCLK = 400 MSPS, WBSFDR
20dB
CENTER 100MHz–100
20MHz/SPAN 200MHz
REF LVL
–5dBm
10kHz
10kHz
RBW
VBW
SWT
RF ATT
UNIT
DELTA [T1]
–63.85dB
100.20040080MHz
Figure 6. FOUT = 40 MHz, FCLK = 400 MSPS, WBSFDR
20dB
CENTER 100MHz–100
20MHz/SPAN 200MHz
REF LVL
–5dBm
10kHz
10kHz
RBW
VBW
SWT
RF ATT
UNIT
DELTA [T1]
–60.96dB
79.75951904MHz
Figure 7. FOUT = 80 MHz FCLK = 400 MSPS, WBSFDR
20dB
CENTER 100MHz
20MHz/SPAN 200MHz
REF LVL
–8dBm
10kHz
10kHz
RBW
VBW
SWT
RF ATT
UNIT
DELTA [T1]
–55.04dB
43.28657315MHz
Figure 8 FOUT = 120 MHz, FCLK = 400 MSPS, WBSFDR
20dB
CENTER 100MHz–100
20MHz/SPAN 200MHz
REF LVL
–8dBm
10kHz
10kHz
RBW
VBW
SWT
RF ATT
UNIT
DELTA [T1]
–50.48dB
–76.95390782MHz
Figure 9. FOUT = 160 MHz, FCLK = 400 MSPS, WBSFDR
20dB
CENTER 1.16MHz
200kHz/SPAN 2MHz
REF LVL
–4dBm
1kHz
1kHz
RBWVBW
SWT
RF ATT
UNIT
DELTA [T1]
–81.87dB
96.19238477kHz
Figure 10. FOUT = 1.1 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
20dB
CENTER 10MHz
200kHz/SPAN 2MHz
REF LVL
–4dBm
1kHz
1kHz
RBW
VBW
SWT
RF ATT
UNIT
DELTA [T1]
–89.33dB
–801.60320641kHz
Figure 11. FOUT = 10 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
20dB
CENTER 39.58MHz–100
200kHz/SPAN 2MHz
REF LVL
–4dBm
1kHz
1kHz
RBW
VBW
SWT
RF ATT
UNIT
DELTA [T1]
–84.92dB
997.99599198kHz
Figure 12. FOUT = 39.9 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
20dB
CENTER 79.76MHz
200kHz/SPAN 2MHz
REF LVL
–4dBm
1kHz
1kHz
RBWVBW
SWT
RF ATT
UNIT
DELTA [T1]
–81.71dB
–601.20240481kHz
Figure 13. FOUT = 80.3 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
20dB
CENTER 119.42MHz
200kHz/SPAN 2MHz
REF LVL
–8dBm
1kHz
1kHz
RBW
VBW
SWT
RF ATT
UNIT
DELTA [T1]
–80.37dB
–1.00200401MHz
Figure 14. FOUT = 120.2 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
20dB
CENTER 159.08MHz
200kHz/SPAN 2MHz
REF LVL
–8dBm
1kHz
1kHz
RBW
VBW
SWT
RF ATT
UNIT
DELTA [T1]
–83.64dB
144.28857715kHz
Figure 15. FOUT = 160 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
Figure 16. Residual Phase Noise with FOUT = 159.5 MHz, FCLK = 400 MSPS
(Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue)
Figure 17. Residual Phase Noise with FOUT = 9.5 MHz, FCLK = 400 MSPS (Green),
4 ×100 MSPS (Red), and 20 × 20 MSPS (Blue)
THEORY OF OPERATION
COMPONENT BLOCKS
DDS Core
The output frequency (fO) of the DDS is a function of the
frequency of the system clock (SYSCLK), the value of the
frequency tuning word (FTW), and the capacity of the accumu-
lator (232 in this case). The exact relationship is given below with
fS defined as the frequency of SYSCLK.
()()3132202/≤≤=FTWwithfFTWfSO 1–222/–323132<<×=FTWwithffSO
The value at the output of the phase accumulator is translated to
an amplitude value via the COS(x) functional block and routed
to the DAC.
In certain applications, it is desirable to force the output signal
to zero phase. Simply setting the FTW to 0 does not accomplish
this; it only results in the DDS core holding its current phase
value. Thus, a control bit is required to force the phase accumu-
lator output to zero.
At power-up, the clear phase accumulator bit is set to Logic 1,
but the buffer memory for this bit is cleared (Logic 0). There-
fore, upon power-up, the phase accumulator remains clear until
the first I/O UPDATE is issued.
Phase-Locked Loop (PLL)
The PLL allows multiplication of the REFCLK frequency. Con-
trol of the PLL is accomplished by programming the 5-bit
REFCLK multiplier portion of Control Function Register No. 2,
Bits <7:3>.
When programmed for values ranging from 0x04 to 0x14
(4 decimal to 20 decimal), the PLL multiplies the REFCLK input
frequency by the corresponding decimal value. However, the
maximum output frequency of the PLL is restricted to
400 MHz. Whenever the PLL value is changed, the user should
be aware that time must be allocated to allow the PLL to lock
(approximately 1 ms).
The PLL is bypassed by programming a value outside the range
of 4 to 20 (decimal). When bypassed, the PLL is shut down to
conserve power.
Clock Input
The AD9859 supports various clock methodologies. Support for
differential or single-ended input clocks and enabling of an
on-chip oscillator and/or a phase-locked loop (PLL) multiplier
are all controlled via user programmable bits. The AD9859 may
be configured in one of six operating modes to generate the
system clock. The modes are configured using the CLKMODE-
SELECT pin, CFR1<4>, and CFR2<7:3>. Connecting the exter-
nal pin CLKMODESELECT to Logic High enables the on-chip
crystal oscillator circuit. With the on-chip oscillator enabled,
users of the AD9859 connect an external crystal to the REFCLK
and REFCLKB inputs to produce a low frequency reference
clock in the range of 20 MHz to 30 MHz. The signal generated
by the oscillator is buffered before it is delivered to the rest of
the chip. This buffered signal is available via the CRYSTAL
OUT pin. Bit CFR1<4> can be used to enable or disable the
buffer, turning on or off the system clock. The oscillator itself is
not powered down in order to avoid long startup times associ-
ated with turning on a crystal oscillator. Writing CFR2<9> to
Logic High enables the crystal oscillator output buffer. Logic
Low at CFR2<9> disables the oscillator output buffer.
Connecting CLKMODESELECT to Logic Low disables the
on-chip oscillator and the oscillator output buffer. With the
oscillator disabled, an external oscillator must provide the
REFCLK and/or REFCLKB signals. For differential operation,
these pins are driven with complementary signals. For single-
ended operation, a 0.1 µF capacitor should be connected
between the unused pin and the analog power supply. With the
capacitor in place, the clock input pin bias voltage is 1.35 V. In
addition, the PLL may be used to multiply the reference
frequency by an integer value in the range of 4 to 20. Table 4
summarizes the clock modes of operation. Note that the PLL
multiplier is controlled via the CFR2<7:3> bits, independent of
the CFR1<4> bit.
Table 4. Clock Input Modes of Operation
DAC Output
The AD9859 incorporates an integrated 10-bit current output
DAC. Unlike most DACs, this output is referenced to AVDD,
not AGND.
Two complementary outputs provide a combined full-scale
output current (IOUT). Differential outputs reduce the amount of
common-mode noise that might be present at the DAC output,
offering the advantage of an increased signal-to-noise ratio. The
full-scale current is controlled by an external resistor (RSET)
connected between the DAC_RSET pin and the DAC ground
(AGND_DAC). The full-scale current is proportional to the
resistor value as follows:
OUTSETIR/19.39=
The maximum full-scale output current of the combined DAC
outputs is 15 mA, but limiting the output to 10 mA provides the
best spurious-free dynamic range (SFDR) performance. The DAC
output compliance range is AVDD + 0.5 V to AVDD – 0.5 V.
Voltages developed beyond this range cause excessive DAC
distortion and could potentially damage the DAC output cir-
cuitry. Proper attention should be paid to the load termination
to keep the output voltage within this compliance range.
Serial I/O Port
The AD9859 serial port is a flexible, synchronous serial communi-
cations port that allows easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O port is com-
patible with most synchronous transfer formats, including both the
Motorola 6905/11 SPI® and Intel® 8051 SSR protocols.
The interface allows read/write access to all registers that configure
the AD9859. MSB first or LSB first transfer formats are supported.
The AD9859’s serial interface port can be configured as a single pin
I/O (SDIO), which allows a 2-wire interface or two unidirectional
pins for in/out (SDIO/SDO), which in turn enables a 3-wire inter-
face. Two optional pins, IOSYNC and CS, enable greater flexibility
for system design in the AD9859.
Register Map and Descriptions
The register map is listed in Table 5.

Partno	Mfg	Dc	Qty	Available	Descript
AD9859YSV	ADI	N/a	2	avai	400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer