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AD9857
CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
REV.B
CMOS 200 MSPS 14-Bit
Quadrature Digital Upconverter
FEATURES
200 MHz Internal Clock Rate
14-Bit Data Path
Excellent Dynamic Performance
80 dB SFDR @ 65 MHz (�100 kHz) AOUT
4�–20� Programmable Reference Clock Multiplier
Reference Clock Multiplier PLL Lock Detect Indicator
Internal 32-Bit Quadrature DDS
FSK Capability
8-Bit Output Amplitude Control
Single-Pin Power-Down Function
Four Programmable, Pin-Selectable Signal “Profiles”
SIN(x)/x Correction (Inverse SINC Function)
Simplified Control Interface
10 MHz Serial, 2- or 3-Wire SPI-Compatible
3.3 V Single Supply
Single-Ended or Differential Input Reference Clock
80-Lead LQFP Surface-Mount Packaging
Three Modes of Operation
Quadrature Modulator Mode
Single-Tone Mode
Interpolating DAC Mode
APPLICATIONS
HFC Data, Telephony, and Video Modems
Wireless Base Station
Agile, L.O. Frequency Synthesis
Broadband Communications
GENERAL DESCRIPTIONThe AD9857 integrates a high-speed Direct Digital Synthesizer
(DDS), a high-performance, high-speed 14-bit digital-to-analog
converter (DAC), clock multiplier circuitry, digital filters, and
other DSP functions onto a single chip, to form a complete
quadrature digital upconverter device. The AD9857 is intended
to function as a universal I/Q modulator and agile upconverter,
single-tone DDS, or interpolating DAC for communications
applications, where cost, size, power dissipation, and dynamic
performance are critical attributes.
The AD9857 offers enhanced performance over the industry-
standard AD9856, as well as providing additional features.
The AD9857 is available in a space-saving surface-mount
package and is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
AD9857FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . . 5
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6
TYPICAL PERFORMANCE CHARACTERISTICS . . . . . 7
Modulated Output Spectral Plots . . . . . . . . . . . . . . . . . . . . 7
Single-Tone Output Spectral Plots . . . . . . . . . . . . . . . . . . . 8
Narrowband SFDR Spectral Plots . . . . . . . . . . . . . . . . . . . 9
Output Constellations . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . 11
Quadrature Modulation Mode . . . . . . . . . . . . . . . . . . . . . 11
Single-Tone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interpolating DAC Mode . . . . . . . . . . . . . . . . . . . . . . . . . 13
SIGNAL PROCESSING PATH . . . . . . . . . . . . . . . . . . . . . 13
Input Data Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Inverse CIC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Fixed Interpolator (4¥) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Programmable (2¥–63¥) CIC Interpolating Filter . . . . . . 16
Quadrature Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DDS Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Inverse SINC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output Scale Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . 17
14-Bit D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reference Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . 18
INPUT DATA PROGRAMMING . . . . . . . . . . . . . . . . . . . 18
Control Interface—Serial I/O . . . . . . . . . . . . . . . . . . . . . . 18
General Operation of the Serial Interface . . . . . . . . . . . . . 18
Instruction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SERIAL INTERFACE PORT PIN DESCRIPTIONS . . . . 21
SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SYNCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MSB/LSB Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Notes Serial Port Operation . . . . . . . . . . . . . . . . . . . . . . . 21
CONTROL REGISTER DESCRIPTION . . . . . . . . . . . . . 22
PROFILE #0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PROFILE #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PROFILE #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PROFILE #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Latency for the Single-Tone Mode . . . . . . . . . . . . . . . . . 25
Other Factors Affecting Latency . . . . . . . . . . . . . . . . . . . 25
EASE OF USE FEATURES . . . . . . . . . . . . . . . . . . . . . . . . 27
Profile Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Setting the Phase of the DDS . . . . . . . . . . . . . . . . . . . . . . 27
Reference Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . 27
PLL Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Single or Differential Clock . . . . . . . . . . . . . . . . . . . . . . . 27
CIC Overflow Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Clearing the CIC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Digital Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Hardware-Controlled Digital Power-Down . . . . . . . . . . . 28
Software-Controlled Digital Power-Down . . . . . . . . . . . . 28
Full Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power Management Considerations . . . . . . . . . . . . . . . . . 29
Equivalent I/O Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 29
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TABLE OF CONTENTS
AD9857
SPECIFICATIONSDAC OUTPUT CHARACTERISTICS
MODULATOR CHARACTERISTICS (65 MHz AOUT)
INVERSE SINC FILTER (Variation in Gain from
(VS = 3.3 V � 5%, RSET = 1.96 k�, External reference clock frequency = 10 MHz with REFCLK Multiplier
enabled at 20�).
AD9857–SPECIFICATIONSSPURIOUS POWER (Off Channel, Measured in
TIMING CHARACTERISTICS
CMOS LOGIC INPUTS
NOTESWake-Up Time refers to recovery from Full-Sleep Mode. The longest time required is for the Reference Clock Multiplier PLL to lock up (if it is being used). The
Wake-Up Time assumes that there is no capacitor on DAC_BP, and that the recommended PLL loop filter values are used. The state of the Reference Clock Multi-
plier lock can be determined by observing the signal on the PLL_LOCK pin.SYSCLK refers to the actual clock frequency used on-chip by the AD9857. If the Reference Clock Multiplier is used to multiply the external reference frequency, the
SYSCLK frequency is the external frequency multiplied by the Reference Clock Multiplier multiplication factor. If the Reference Clock Multiplier is not used, the
SYSCLK frequency is the same as the external REFCLK frequency.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9857 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*Maximum Junction Temperature . . . . . . . . . . . . . . . . .150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . .–0.7 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . .5 mA
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . .–40°C to +85°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . .300°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16°C/W
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
ORDERING GUIDE
EXPLANATION OF TEST LEVELS
Test Level100% production tested.
II.100% production tested at 25°C and sample tested at spe-
cific temperatures.
III.Sample tested only.
IV.Parameter is guaranteed by design and characterization
testing.Parameter is a typical value only.
VI.Devices are 100% production tested at 25°C and guaran-
teed by design and characterization testing for industrial
operating temperature range.
PIN CONFIGURATION
DIFFCLKEN
AGND
AVDD
AGND
PLL_FILTER
AVDD
AGND
DAC_RSET
DAC_BP
AVDD
AGND
IOUT
IOUT
AGND
AVDD
AGND
D13
D12
D11
D10
DVDD
DVDD
DVDD
DGND
DGND
DGND
TxENABLEPDCLK/FUDDGNDDGNDDGNDDVDDDVDDDVDDDGNDDGNDDGNDCIC_OVRFLPLL_LOCKRESETDPDAGNDAVDDREFCLKREFCLKAGND
PS1PS0
SDIO
SDO
AD9857
PIN FUNCTION DESCRIPTIONSModulated Output Spectral PlotsTPC 1.QPSK at 42 MHz and 2.56MS/s; 10.24 MHz
External Clock with REFCLK Multiplier = 12, CIC
Interpolation Rate = 3, 4� Oversampled Data
TPC 2.64-QAM at 28 MHz and 6 MS/s; 36 MHz External
Clock with REFCLK Multiplier = 4, CIC Interpolation
Rate = 2, 3� Oversampled Data
TPC 3.16-QAM at 65 MHz and 1.28 MS/s; 10.24 MHz
External Clock with REFCLK Multiplier = 18, CIC
Interpolation Rate = 9, 4� Oversampled Data
TPC 4.256-QAM at 38 MHz and 6 MS/s; 48 MHz External
Clock with REFCLK Multiplier = 4, CIC Interpolation
Rate = 2, 4� Oversampled Data
AD9857
Single-Tone Output Spectral PlotsTPC 5.21 MHz Single-Tone Output
TPC 6.65 MHz Single-Tone Output
TPC 7.42 MHz Single-Tone Output
TPC 8.79 MHz Single-Tone Output
Narrowband SFDR Spectral PlotsTPC 9.70.1 MHz Narrowband SFDR, 10 MHz External
Clock with REFCLK Multiplier = 20
TPC 10.70.1 MHz Narrowband SFDR, 200 MHz External
Clock with REFCLK Multiplier Disabled
AD9857TPC 11. QPSK, 65 MHz, 2.56 MS/s
TPC 12. 64-QAM, 42 MHz, 6 MS/s
TPC 13. GMSK Modulation, 13 MS/s
TPC 14. 16-QAM, 65 MHz, 2.56 MS/s
TPC 15. 256-QAM, 42 MHz, 6 MS/s
Output Constellations
MODES OF OPERATIONThe AD9857 has three operating modes:Quadrature Modulation Mode (Default)Single-Tone ModeInterpolating DAC Mode
Mode selection is accomplished by programming a control register
via the Serial Port. The Inverse SINC Filter and output scale mul-
tiplier are available in all three modes.
Quadrature Modulation ModeIn Quadrature Modulation Mode, both the I and Q data paths
are active. A block diagram of the AD9857 operating in the
Quadrature Modulation Mode is shown in Figure 1.
In Quadrature Modulation Mode, the PDCLK/FUD pin is an
output and functions as the Parallel Data Clock (PDCLK), which
serves to synchronize the input of data to the AD9857. In this
mode, the input data must be synchronized with the rising edge
of PDCLK. The PDCLK operates at twice the rate of either the
I or Q data path. This is due to the fact that the I and Q data must
be presented to the parallel port as two 14-bit words multiplexed
in time. One I word and one Q word together comprise one internal
sample. Each sample is propagated along the internal data path-
way in parallel fashion.
The DDS core provides a quadrature (sin and cos) local oscilla-
tor signal to the quadrature modulator, where the I and Q data
are multiplied by the respective phase of the carrier and summed
together, to produce a quadrature-modulated data stream.
All of this occurs in the digital domain, and only then is the digital
data stream applied to the 14-bit DAC to become the quadrature-
modulated analog output signal.
Figure 1.Quadrature Modulation Mode
AD9857
Single-Tone ModeA block diagram of the AD9857 operating in the Single-Tone
Mode is shown in Figure 2. In the Single-Tone Mode, both
the I and Q data paths are disabled from the 14-bit Parallel
Data Port up to and including the modulator. The PDCLK/
FUD pin is an input and functions as a Frequency Update
(FUD) control signal. This is necessary because the frequency
tuning word is programmed via the asynchronous serial port.
The FUD signal causes the new frequency tuning word to
become active.
In Single-Tone Mode, the cosine portion of the DDS serves as the
signal source. The output signal consists of a single frequency as
determined by the tuning word stored in the appropriate control
register, per each profile.
In the Single-Tone Mode, no 14-bit parallel data is applied to the
AD9857. The internal DDS core is used to produce a single
frequency signal according to the tuning word. The single-
tone signal then moves toward the output, where the Inverse
SINC Filter and the output scaling can be applied. Finally,
the digital single-tone signal is converted to the analog domain
by the 14-bit DAC.
Figure 2.Single-Tone Mode
Interpolating DAC ModeA block diagram of the AD9857 operating in the Interpolating
DAC Mode is shown in Figure 3. In this mode, the DDS and
modulator are both disabled and only the I data path is active.
The Q data path is disabled from the 14-bit Parallel Data Port
up to and including the modulator.
As in the Quadrature Modulation Mode, the PDCLK pin is an
output and functions as a clock which serves to synchronize the
input of data to the AD9857. Unlike the Quadrature Modulation
Mode, however, the PDCLK operates at the rate of the I data path.
This is because only I data is being presented to the parallel port
as opposed to the interleaved I/Q format of the Quadrature
Modulation Mode.
In the Interpolating DAC mode, the baseband data supplied at the
parallel port remains at baseband at the output; i.e., no modulation
takes place. However, a sample rate conversion takes place based
on the programmed interpolation rate. The interpolation hardware
performs the necessary signal processing required to eliminate the
aliased images at baseband that would otherwise result from a
sample rate conversion. The interpolating DAC function is effec-
tively an oversampling operation with the original input spectrum
intact but sampled at a higher rate.
SIGNAL PROCESSING PATHTo better understand the operation of the AD9857 it is helpful to
follow the signal path from input, through the device, to the
output, examining the function of each block (refer to the Func-
tional Block Diagram). The input to the AD9857 is a 14-bit
parallel data path. This assumes that the user is supplying the
The AD9857 demultiplexes the interleaved I and Q data into two
separate data paths inside the part. This means that the input
sample rate (fDATA), the rate at which 14-bit words are presented to
the AD9857, must be 2× the internal I/Q Sample Rate (fIQ),
the rate at which the I/Q pairs are processed. In other words,
fDATA = 2 × fIQ.
From the input demultiplexer to the Quadrature Modulator, the
data path of the AD9857 is a dual I/Q path.
All timing within the AD9857 is provided by the internal System
Clock (SYSCLK) signal. The externally provided Reference
Clock signal may be used as is (1×), or multiplied by the internal
Clock Multiplier (4× –20×) to generate the SYSCLK. All other
internal clocks and timing are derived from the SYSCLK.
Input Data AssemblerIn the Quadrature Modulation or Interpolating DAC Modes, the
device accepts 14-bit, two’s complement data at its parallel data
port. The timing of the data supplied to the parallel port may
be easily facilitated with the PDCLK/FUD pin of the AD9857,
which is an output in the Quadrature Modulation Mode and the
Interpolating DAC mode. In the Single-Tone Mode, the same
pin becomes an input to the device and serves as a Frequency
Update (FUD) strobe.
Frequency control words are programmed into the AD9857 via
the serial port (see the Control Register Description). Since the
serial port is an asynchronous interface, when programming new
frequency tuning words into the on-chip profile registers, the
AD9857’s internal frequency synthesizer must be synchronized
with external events. The purpose of the FUD input pin is to
Figure 3.Interpolating DAC Mode
AD9857set the PLL Lock Control bit in the appropriate Control Register.
Data supplied by the user to the 14-bit Parallel Port is latched
into the device coincident with the rising edge of the PDCLK.
In the Quadrature Modulation Mode, the rising edge of the
TxENABLE signal is used to synchronize the device. While
TxENABLE is in the Logic 0 state, the device ignores the 14-bit
data applied to the parallel port and allows the internal data path to
be flushed by forcing 0s down the I and Q data pathway. On the
rising edge of TxENABLE, the device is ready for the first I word.
The first I word is latched into the device coincident with the
rising edge of PDCLK. The next rising edge of PDCLK latches in
a Q word, etc., until TxENABLE is set to a Logic 0 state by the user.
When in the Quadrature Modulation Mode, it is important that
the user ensure that an even number of PDCLK intervals are
observed during any given TxENABLE period. This is because
the device must capture both an I and a Q value before the data
can be processed along the internal data pathway.
The timing relationship between TxENABLE, PDCLK, and
DATA is shown in Figures 4 and 5.
Figure 4.14-Bit Parallel Port Timing Diagram—Quadrature Modulation Mode
Figure 5.14-Bit Parallel Port Timing Diagram—Interpolating DAC Mode
Table I.Parallel Data Bus Timing(see the Profile section) to be transferred to the accumulator of
the DDS, thus starting the frequency synthesis process.
After loading the frequency tuning word to a profile, a FUD signal
is not needed when switching between profiles using the two profile
select pins (PS0, PS1). When switching between profiles, the
frequency tuning word in the profile register becomes effective.
In the Quadrature Modulation Mode, the PDCLK rate is twice
the rate of the I (or Q) data rate. The AD9857 expects interleaved
I and Q data words at the parallel port with one word per PDCLK
rising edge. One I word and one Q word together comprise one
internal sample. Each sample is propagated along the internal
data pathway in parallel.
In the Interpolating DAC Mode, however, the PDCLK rate is
the same as the I data rate since the Q data path is inactive. In
this mode, each PDCLK rising edge latches a data word into the
I data path.
The PDCLK is provided as a continuous clock (i.e., always
active). However, the assertion of PDCLK may be optionally
qualified internally by the PLL Lock Indicator if the user elects to
Inverse CIC FilterThe Inverse CIC (Cascaded Integrator Comb) Filter precompen-
sates the data to offset the slight attenuation gradient imposed by
the CIC Filter (see the Programmable (2× – 63×) CIC Interpolat-
ing Filter section). The I (or Q) data entering the first half-band
filter occupies a maximum bandwidth of one-half fDATA as defined
by Nyquist (where fDATA is the sample rate at the input of the first
half-band filter). This is shown graphically in Figure6.
Figure 6.CIC Filter Response
If the CIC Filter is employed, the inband attenuation gradient
could pose a problem for those applications requiring an extremely
flat pass band. For example, if the spectrum of the data as supplied
to the AD9857 I or Q path occupies a significant portion of the
one-half fDATA region, the higher frequencies of the data spectrum
will receive slightly more attenuation than the lower frequencies
(the worst-case overall droop from f = 0 to one-half fDATA is
< 0.8 dB). This may not be acceptable in certain applications. The
Inverse CIC Filter has a response characteristic that is the inverse
of the CIC Filter response over the one-half fDATA region.
The net result is that the product of the two responses yields in an
extremely flat pass band, thereby eliminating the inband attenua-
tion gradient introduced by the CIC Filter. The price to be paid is
a slight attenuation of the input signal of approximately 0.5dB
for a CIC interpolation rate of 2 and 0.8 dB for interpolation rates
of 3 to 63.
The Inverse CIC Filter is implemented as a digital FIR Filter
with a response characteristic that is the inverse of the Program-
mable CIC Interpolator. The product of the two responses yields a
nearly flat response over the baseband Nyquist bandwidth. The
Inverse CIC Filter provides frequency compensation that yields a
response flatness of ±0.05 dB over the baseband Nyquist band-
width, allowing the AD9857 to provide excellent SNR over its
performance range.
The Inverse CIC Filter can be bypassed by setting Control Register
06h<0>. It is automatically bypassed if the CIC interpolation rate
is 1×. Whenever this stage is bypassed, power to the stage is shut
off, thereby reducing power dissipation.
Fixed Interpolator (4�)This block is a fixed 4× interpolator. It is implemented as two
half-band filters. The output of this stage is the original data
upsampled by 4×.
Before presenting a detailed description of the half-band filters,
recall that in the case of the Quadrature Modulation Mode the
input data stream is representative of complex data; i.e., two
input samples are required to produce one I/Q data pair. The
I/Q sample rate is one-half the input data rate. The I/Q sample
rate (the rate at which I or Q samples are presented to the input
of the first half-band filter) will be referred to as fIQ. Since the
AD9857 is a quadrature modulator, fIQ represents the baseband
of the internal I/Q sample pairs. It should be emphasized here
that fIQ is not the same as the baseband of the user’s symbol rate
data, which must be upsampled before presentation to the AD9857
(as will be explained later). The I/Q sample rate (fIQ) puts a
limit on the minimum bandwidth necessary to transmit the
fIQ spectrum. This is the familiar Nyquist limit and is equal to
one-half fIQ, hereafter referred to as fNYQ.
Together, the two half-band filters provide a factor-of-four increase
in the sampling rate (4 × fIQ or 8 × fNYQ). Their combined insertion
loss is 0.01 dB, so virtually no loss of signal level occurs through
the two half-band filters. Both half-band filters are linear phase
filters, so that virtually no phase distortion is introduced within
the pass band of the filters. This is an important feature as phase
distortion is generally intolerable in a data transmission system.
The half-band filters are designed so that their composite perfor-
mance yields a usable pass band of 80% of the baseband Nyquist
frequency (0.2 on the frequency scale below). Within that pass
band, the ripple will not exceed 0.002 dB. The stopband extends
from 120% to 400% of the baseband Nyquist frequency (0.3 to
1.0 on the frequency scale below) and offers a minimum of 85dB
attenuation. The composite response of the two half-band
filters together are shown in Figures 7 and 8.
FREQUENCY0.20.4
SAMPLE RATEFigure 7.Half-Band 1 and 2 Frequency Response;
Frequency Relative to HB1 Output Sample Rate
AD9857Figure 8.Combined Half-Band 1 and 2 Pass Band Detail;
Frequency Relative to HB1 Output Sample Rate
The usable bandwidth of the filter chain puts a limit on the
maximum data rate that can be propagated through the AD9857.
A look at the pass band detail of the half-band filter response
(Figure 8) indicates that in order to maintain an amplitude
error of no more than 1 dB, signals are restricted to having a
bandwidth of no more than about 90% of fNYQ. Thus, to keep
the bandwidth of the data in the flat portion of the filter pass
band, the user must oversample the baseband data by at least a
factor of two prior to presenting it to the AD9857. Note that
without oversampling, the Nyquist bandwidth of the baseband
data corresponds to the fNYQ. Because of this, the upper end of
the data bandwidth will suffer 6 dB or more of attenuation
due to the frequency response of the half-band filters. Further-
more, if the baseband data applied to the AD9857 has been
pulse shaped, there is an additional concern.
Typically, pulse shaping is applied to the baseband data via a
filter having a raised cosine response. In such cases, an α value
is used to modify the bandwidth of the data where the value of α
is such that 0 < α < 1. A value of 0 causes the data bandwidth to
correspond to the Nyquist bandwidth. A value of 1 causes the data
bandwidth to be extended to twice the Nyquist bandwidth. Thus,
with 2× oversampling of the baseband data and α = 1, the Nyquist
bandwidth of the data will correspond with the I/Q Nyquist
bandwidth. As stated earlier, this results in problems near the
upper edge of the data bandwidth due to the roll-off attenuation of
the half-band filters. Figure 9 illustrates the relationship between
α and the bandwidth of raised cosine shaped pulses. The problem
area is indicated by the shading in the tail of the pulse with α=1
which extends into the roll-off region of the half-band filter.
The effect of raised cosine filtering on baseband pulse bandwidth,
and the relationship to the half-band filter response are shown in
Figure 9.
Figure 9.Effect of Alpha
Programmable (2� to 63�) CIC Interpolating FilterThe Programmable Interpolator is implemented as a CIC Filter.
It is programmable by a 6-bit control word, giving a range of 2×
to 63× interpolation. This interpolator has a low-pass frequency
characteristic that is compensated by the Inverse CIC Filter.
The Programmable Interpolator can be bypassed to yield a 1× (no
interpolation) configuration by setting the bit in the appropri-
ate control register, per each profile. Whenever the Programmable
Interpolator is bypassed (1× CIC rate), power to the stage is
removed. If the Programmable Interpolator is bypassed, the
Inverse CIC Filter (see above) is automatically bypassed, since
its compensation is not needed in this case.
The output of the Programmable Interpolator is the data from
the 4× interpolator upsampled by an additional 2× to 63×, accord-
ing to the rate chosen by the user. This results in the input data
being upsampled by a factor of 8× to 252×.
The transfer function of the CIC Interpolating Filter is:(1)
where R is the interpolation rate, and f is the frequency relative
to SYSCLK.
