AD9853AS Fast Delivery |IC PHOENIX CO.,LIMITED

AD9853AS ,Programmable Digital OPSK/16-QAM ModulatorSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*EXPLANATION OF TEST LEVELS ..
AD9854ASQ ,CMOS 300 MHz Quadrature Complete-DDSCHARACTERISTICSI and Q DAC Quad. Phase Error 25

AD9853AS
Programmable Digital OPSK/16-QAM Modulator
REV.C
Programmable Digital
QPSK/16-QAM Modulator
FUNCTIONAL BLOCK DIAGRAM
SINECOSINE
XOR
AD985310
AOUT
GAIN
CONTROL TO
DRIVER AMP
RESETTXENABLEFEC
ENABLE/
DISABLE
REF CLOCK IN
SERIAL
DATA IN
SERIAL CONTROL BUS:
32-BIT OUTPUT FREQUENCY TUNING WORD
INPUT DATA RATE/MODULATION FORMAT
FEC/RANDOMIZER/PREAMBLE ENABLE/CONFIGURATION
FIR FILTER COEFFICIENTS
REF CLOCK MULTIPLIER ENABLE
I/Q PHASE INVERT
SLEEP MODE
TO LP FILTER
AND AD8320
CABLE DRIVER
AMPLIFER
FEATURES
Universal Low Cost Solution for HFC Network
Return-Channel TX Function: 5 MHz–42 MHz/
5 MHz–65 MHz
165 MHz Internal Reference Clock Capability
Includes Programmable Pulse-Shaping FIR Filters and
Programmable Interpolating Filters
FSK/QPSK/DQPSK/16-QAM/D16-QAM Modulation
Formats
63 Internal Reference Clock Multiplier
Integrated Reed-Solomon FEC Function
Programmable Randomizer/Preamble Function
Supports Interoperable Cable Modem Standards
Internal SINx/x Compensation
>50 dB SFDR @ 42 MHz Output Frequency (Single Tone)
Controlled Burst Mode Operation
+3.3 V to +5 V Single Supply Operation
Low Power: 750 mW @ Full Clock Speed (3.3 V Supply)
Space Saving Surface Mount Packaging
APPLICATIONS
HFC Data, Telephony and Video Modems
Wireless LAN
GENERAL DESCRIPTION
The AD9853 integrates a high speed direct-digital synthesizer
(DDS), a high performance, high speed digital-to-analog con-
verter (DAC), digital filters and other DSP functions onto a
single chip, to form a complete and flexible digital modulator
device. The AD9853 is intended to function as a modulator in
network applications such as interactive HFC, WLAN and
MMDS, where cost, size, power dissipation, functional integra-
tion and dynamic performance are critical attributes.
The AD9853 is fabricated on an advanced CMOS process and
it sets a new standard for CMOS digital modulator performance.
The device is loaded with programmable functionality and
provides a direct interface port to the AD8320, digitally-
programmable cable driver amplifier. The AD9853/AD8320
chipset forms a highly integrated, low power, small footprint
and cost-effective solution for the HFC return-path requirement
and other more general purpose modulator applications.
The AD9853 is available in a space saving surface mount pack-
age and is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
AD9853–SPECIFICATIONS
(VS = +3.3 V 6 5%, RSET = 3.9 kV, Reference Clock Frequency = 20.48 MHz with
63 REFCLK Enabled, Symbol Rate = 2.56 MS/s, a = 0.25, unless otherwise noted)
AD9853
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9853 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
NOTES
1Reference clock = 28 MHz with clock multiplier enabled; supply voltage = +5 V.
2Maximum values are obtained under worst case operating modes. Typical values are valid for most applications.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level–100% Production Tested.
III–Sample Tested Only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–Devices are 100% production tested at +25°C and
guaranteed by design and characterization testing for
industrial operating temperature range.
ABSOLUTE MAXIMUM RATINGS*
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (10 sec Soldering) . . . . . . . . . . . . +300°C
MQFP qJA Thermal Impedance . . . . . . . . . . . . . . . . . 36°C/W
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect device
reliability.
ORDERING GUIDE
AD9853
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
44-Lead Metric Quad Flatpack
(S-44A)
AVDD
DAC BASELINE
AVDD
NC
PLL GND
PLL GND
AGND
CA ENABLE
PLL VCC
RESET
TEST DATA OUT
PLL FILTER
TEST DATA
ENABLE
DAC RSET
DVDD
TEST DATA IN
AGND
TEST LATCH
DGND
TEST CLK
IOUTB
IOUT
DVDD
AGND
DGNDDGND
DGND
DVDD
CONTROL
BUS CLOCK
DVDD
CONTROLBUS DATA IN
FEC ENABLE
ADDRESS BIT
DGND
NC = NO CONNECT
DVDD
DGND
DGND
TEST DATAOUT
TEST DATA OUT
ENABLE
DATA INREF CLK INCA CLOCKCA DATA
ADDRESS BIT
Table I.Modulator Function Description
*In FSK mode, F0:F1 are direct DDS Cosine output. The two interpolator stages of the AD9853 are not used in the FSK mode and should be programmed for
maximum interpolation rates to reduce unnecessary current consumption. This means that Interpolator #1 should be set to a decimal value of 31, and Interpolator
#2 should be set to decimal value of 63. This is easily accomplished by programming Registers 12 and 13 (hex) with the values of FF (hex).
AD9853
Table II.Control Register Functional Assignment
NOTESThe 8-bit Register Address is preceded by an 8-bit Device Address, which is given by
000001XY, where the value of Bits X and Y are determined as follows:This register must be loaded with a nonzero value even if the RS encoder has been
disabled by setting T = 0 in register 01h.Unused regions are don’t care bit locations.
4If a preamble is not used this register must be initialized to a value of 0 by the user.
6Readback of register 15h results in a value that is 2· the actual programmed value.
This is a design error in the readback function.
7Assertion of RESET (Pin 32) sets the contents of this register to 0.Registers 0h–48h may be written to using a single register address followed by a
contiguous data sequence (see Figure 27). Register 49h, however, must be written to
individually; i.e., a separately addressed 8-bit data sequence.
Modulated Output Spectrum with 3.3 V Supply, a = 0.25, 20.48 MHz REFCLK
START 0HzSTOP 60MHz6MHz/
–50
Figure 1.QPSK, 320 kb/s, AOUT = 10 MHz
–100START 0HzSTOP 60MHz6MHz/
–50
Figure 2.QPSK, 640 kb/s, AOUT = 20 MHz
START 0HzSTOP60 MHz6MHz/
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 10dB
REF LVL = –20dBm
Figure 3.QPSK, 1.28 Mb/s, AOUT = 42 MHz
–100START 0HzSTOP 60MHz6MHz/
–50
Figure 4.QPSK, 1.28 Mb/s, AOUT = 10 MHz
START 0HzSTOP 60MHz6MHz/
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 10dB
REF LVL = –20dBm
Figure 5.QPSK, 2.56 Mb/s, AOUT = 20 MHz
START 0HzSTOP60 MHz6MHz/
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 10dB
REF LVL = –20dBm
Figure 6.QPSK, 5.12 Mb/s, AOUT = 42 MHz
AD9853
START 0HzSTOP 60MHz6MHz/
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 30dB
REF LVL = 0dBm
Figure 8.AOUT = 1 MHz
START 0HzSTOP 60MHz6MHz/
RBW = 3kHz
VBW = 3kHz
SWT = 17s
RF ATT = 30dB
REF LVL = 0dBm
Figure 9.AOUT = 42 MHz
Modulated Output Spectrum with 5 V Supply, a = 0.25, 27.5 MHz REFCLK
–10START 0HzSTOP 80MHz8MHz/
–50
Figure 7.QPSK, 1.375 Mb/s, AOUT = 65 MHz
Single Tone Output Spectrum with +3.3 V Supply, 20.48 MHz REFCLK
START 0HzSTOP 60MHz6MHz/
–50
Figure 11.AOUT = 20 MHz
–100CENTER 40HzSPAN 80MHz8MHz/
–50
Figure 12.AOUT = 65 MHz
(+5 V Supply, 27.5 MHz REFCLK)
–100START 0 HzSTOP 80 MHz8 MHz/
–50
Figure 10.QPSK, 5.5 Mb/s, AOUT = 65 MHz
Output Phase Noise Plots, AOUT = 40 MHz
–100CENTER 40HzSPAN 10MHz1kHz/
–50
Figure 13.63 REFCLK Enabled
CH PWR = –6.98dBm
ACP UP = –44.95dBm
ACP LOW = –44.66dBm
ALT1 UP = –65.96dBm
ALT1 LOW = –65.99dBm
Figure 15.Adjacent Channel Power, AOUT = 30 MHz,
2.56 MS/s, Channel BW = 3.2 MHz (a = 0.25)
–50
Figure 14.63 REFCLK Disabled
AD9853
SYMBOLS
REF LVL
–8dBm
CF 42MHz MEAS SIGNAL
SR 1.28MHz EYE [1]
DEMOD 16QAM
Figure 18.16-QAM Modulation
–1.51.5REAL
REF LVL
–8dBm
CF 42MHz MEAS SIGNAL
SR 1.28MHz CONSTELLATION
DEMOD 16QAM
Figure 19.16-QAM Modulation
SYMBOLS
REF LVL
–7dBm
CF 42MHz MEAS SIGNAL
SR 1.28MHz EYE [1]
DEMOD QPSK
Figure 16.QPSK Modulation
–1.51.5REAL
REF LVL
–7dBm
CF 42MHz MEAS SIGNAL
SR 1.28MHz CONSTELLATION
DEMOD QPSK
Figure 17.QPSK Modulation
Typical Plots of Eye Diagrams and Constellations
MAX CLOCK RATE – MHz
AMBIENT TEMP –
110115170120125130135140145150155160165
Figure 20.Max CLK Rate vs. Ambient Temperature
(To Ensure Max Junction Temp is Not Exceeded)
BIT RATE – Mb/s
POWER – Watts
2.2
Figure 21.Power Consumption vs. Bit Rate
BIT RATE – Mb/s
SPURIOUS IN-BAND EMISSION – dBc
–40
Figure 22.Spurious Emission vs. Bit Rate vs. AOUT
BIT RATE – Mb/s
POWER – Watts
0.60
Figure 23.PWR Consumption vs. Bit Rate
BURST MODE DUTY CYCLE – %
POWER – Watts
2.5
Figure 24.Power Consumption vs. Burst Duty Cycle
BIT RATE – Mb/s
SPURIOUS IN-BAND EMISSION – dBc
Figure 25.Spurious Emission vs. Bit Rate vs. AOUT
AD9853
NOTES ON BURST TRANSMISSION OPERATION:
1. PACKET LENGTH = NUMBER OF INFORMATION BYTES, K
2. IN FEC MODE TXENABLE MUST BE KEPT HIGH FOR N 3 (K+2T) BYTES WHERE N IS THE NUMBER OF CODEWORDS
3. IF NECESSARY, ZERO FILL THE LAST CODEWORD TO REACH ASSIGNED K DATA BYTES PER CODEWORD
4. THE INPUT DATA IS SAMPLED AT THE BIT RATE FREQUENCY (fB) WITH THE FIRST SAMPLE TAKEN AT SECONDS AFTER THE
RISING EDGE OF TXENABLE
5. PREAMBLE DELAY =
6. DATA RATE MUST BE EXACT SUB-MULTIPLE OF REFERENCE CLOCK.
2 3 (fB)
(# OF PREAMBLE BITS)
(BIT RATE FREQUENCY)
FRAME STRUCTURE:MIN TXENABLE LOW TIME = PREAMBLE + 8 SYMBOLS. (EQUATES TO 8 SYMBOLS
MINIMUM SPACING BETWEEN BURSTS WITH NO CHANGE IN PROFILE)
TXENABLE
TXENABLE TO
AOUT LATENCY
DATA IN
INTERNAL CODE-
WORD STRUCTURE
AT R-S OUTPUT
FRAME STRUCTURE FOR MULTIPLE CODE WORDS OR CONTINOUS TRANSMISSION:
TXENABLE
DATA IN
INPUT DATA PROCESSING:
TXENABLE
DATA
PACKET
AND
FEC PARITY
COMPLETE FRAME AS PRESENTED TO MODULATOR ENCODER:
INTERNAL
BIT CLOCK
DATA IN
ENCODER
INPUT
PREAMBLE LENGTH = 96 BITS MAXIMUM
DURING THIS INTERVAL THE DATA IS R-S ENCODED, RANDOMIZED, AND
DELAYED TO SYNCHRONIZE WITH THE END OF THE PREAMBLE DATA.
Figure 26.Data Framing and Processing
WRITEREADLSB = 0LSB = 1
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START CONDITION
P = STOP CONDITIONA(M) = NO ACKNOWLEDGE BY MASTER
Figure 27.Serial Control Bus—Read and Write SequencesMSBLSB
0 = WRITE / 1 = READ
ADDRESS CONTROL
(SET VIA DEVICE PIN 6)
Figure 28.Serial Control Bus—8-Bit Device Address Detail
Figure 29.FEC Enable/Disable Timing Diagram
AD9853
DIRECT
CONTROL
LINES
DATA IN
REF
CLOCK IN
Figure 32.Basic Implementation of AD9853 Digital Modulator and AD8320 Programmable Cable Driver Amplifier in
Return-Path Application
RESETCONTROL BUS
TXENABLE
DAC OUT
tRL: MINIMUM RESET LOW TIME = 10ns
tDL: DATA LATENCY = 6 SYMBOLS
NOTE 1. DURING THIS INTERVAL ALL CONTROL BUS REGISTERS MUST BE PROGRAMMED.
NOTE 2. DURING THIS INTERVAL THE CONTROL REGISTER (48h) MAY NEED TO BE REPROGRAMMED DUE TO BEING CLEARED
BY THE PRECEDING RESET PULSE.
NOTE 3. THREE RESETS ARE REQUIRED TO ENSURE THAT THE DATA PATH IS ZERO'D.
START UP
SEQUENCE
Figure 31.Recommended Start-Up Sequence
THEORY OF OPERATION
The AD9853 is a highly integrated modulator function that has
been specifically designed to meet the requirements of the HFC
upstream function for both interoperable and proprietary system
implementations. The AD8320 is a companion cable driver
amplifier with a digitally-programmable gain function, that
interfaces to the AD9853 modulator and directly drives the
cable plant with the modulated carrier. Together, the AD9853
and AD8320 provide an easily implementable transmitter solu-
tion for the HFC return-path requirement.
CONTROL AND DATA INTERFACE
As shown in the device’s block diagram on the front page, the
various transmit parameters, which include the input data rate,
modulation format, FEC and randomizer configurations, as well
as all the other modulator functions, are programmed into the
AD9853 via a serial control bus. The AD8320 cable driver amp
gain can be programmed directly from the AD9853 via a 3-wire
bus by writing to the appropriate AD9853 register. The AD9853
also contains dedicated pins for FEC enable/disable and a RESET
function.
Note: TXENABLE pin must be held low for the duration of all
serial control bus operations.
The AD9853’s serial control bus consists of a bidirectional data
line and a clock line. Communication is initiated upon a start
condition, which is defined as a high-to-low transition of the
data line while the clock is held high. Communication terminates
upon a stop condition, which is defined as a low-to-high transi-
tion in the data line while the clock is held high. Ordinarily, the
data line transitions only while the clock line is low to avoid a
start or stop condition. Data is always written or read back in
8-bit bytes followed by a single acknowledge bit. The micro-
controller or ASIC (i.e., the bus master) transfers eight data bits
and the AD9853 (i.e., the slave) issues the acknowledge bit. The
acknowledge bit is active low and is clocked out on every ninth
clock pulse. The bus master must three-state the data line dur-
ing the ninth clock pulse and allow the AD9853 to pull it low.
A valid write sequence consists of a minimum of three bytes.
This means 27 clock pulses (three bytes with nine clock pulses
each) must be provided by the bus master. The first byte is a
chip address byte that is predefined except for Bit Positions 1
and 0. Bit Positions 7, 6, 5, 4 and 3 must be zero. Bit Position 2
must be a one. Bit 1 is set according to the external address pin
on the AD9853 (1 if the pin is connected to +VS; 0 if the pin
is grounded). Bit 0 is set to 1 if a read operation is desired, 0 if a
write operation is desired. The second byte is a register address
with valid addresses between 00h and 49h. An address which is
outside of this range will not be acknowledged. The third byte is
data for the address register. Multiple data bytes are allowed
and loaded sequentially. That is, the first data byte is written to
the addressed register and any subsequent data bytes are written
to subsequent register addresses. It is permissible to write all
registers by issuing a valid chip address byte, then an address
byte of 00h and then 72 (48h) data bytes. Address 49h must be
written independently, that is, not in conjunction with any other
address.
read/write bit set to 0, and the readback register address. After
the slave provides an acknowledge at the end of the register
address, the master must present a START condition on the
bus, followed by the Chip Address Byte with the read/write bit
set to a 1. The slave proceeds to provide an acknowledge. Dur-
ing the next eight clocks the slave will write to the bus from the
register address. The master must provide an acknowledge on
the ninth clock of this byte. Any subsequent clocks from the
master will force the slave to read back from subsequent regis-
ters. At the end of the read-back cycle, the MASTER must force
a “no-acknowledge” and then a STOP condition. This will take
the SLAVE out of read-back mode. Not all of the serial control
bus registers can be read back. Registers (06h–11h) and (1Eh–
47h) are write only. Also, like the writing procedure, register
49h must be read from independently.
INPUT DATA SYNCHRONIZATION
The serial input data interface consists of two pins, the serial
data input pin and a TXENABLE pin. The input data arrives at
the bit rate and is framed by the TXENABLE signal as shown in
Figure 26. A high frequency sampling clock continuously
samples the TXENABLE signal to detect the rising edge. Once
the rising edge of TXENABLE is detected, an internal sampler
strobes the serial data at the correct point in time relative to the
positive TXENABLE transition and then continues to sample at
the correct interval based on the programmed Input Data rate.
For proper synchronization of the AD9853, 1) the input burst
data must be accurately framed by TXENABLE and 2) the
input data rate must be an exact even submultiple of the system
clock. Typically this will require that the input data rate clock be
synchronized with reference clock.
REED-SOLOMON ENCODER
The AD9853 contains a programmable Reed-Solomon (R-S)
encoder capable of generating an (N, K) code where N is the
code word length and K is the message length.
Error correction becomes vital to reliable communications when
the transmission channel conditions are less than ideal. The
original message can be precisely reconstructed from a cor-
rupted transmission as long as the number of message errors is
within the encoder’s limits. When forward error correction
(FEC) is engaged, either through the serial control interface
bus or hardware (logic high at Pin 5), it is implemented using
the following MCNS-compatible field generator and primitive
polynomials:
Primitive Polynomial:p(x) = x8 + x4 + x3 + x2 + 1
Code Generator Polynomial:g(x) = (x + a0)(x + a1)(x + a2)
. . . (x + a2t – 1)
The code-word structure is defined as follows:
N = K + 2t (bytes)
where:
N =code-word length
K =message length (in bytes), programmable from 16–255
t =number of byte errors that can be corrected programmable
from 0–10.
AD9853
receive end. The values actually programmed on the serial con-
trol bus are “K” and “t,” which will define N as shown in the
above code-word structure equation. As can be seen from the
code-word structure equation, two check bytes are required to
correct each byte error. Setting t = 0 and K > 0 will bypass the
Reed-Solomon encoding process.
Since Reed-Solomon works on bytes of information and not
bits, a single byte error can be as small as one inverted bit out of
a byte, or as large as eight inverted bits of one byte; in either
instance the result is one byte error. For example, if the value
“t” is specified as 5, the R-S FEC could be correcting as many
as 40, or as few as 05, erroneous bits, but those errors must be
contained in 5 message bytes. If the errors are spread among
more than five bytes, the message will not be fully error corrected.
When using the R-S encoder, the message data needs to be
partitioned or “gapped” with “don’t care” data for the time
duration of the check bytes as shown in the timing diagram of
Figure 26. During the intervals between message data, the de-
vice ignores data at the input.
The position of the R-S encoder in the coding data path can be
switched with the randomizer by exercising Register 1, Bit D3,
via the serial control bus.
RANDOMIZER FUNCTION
The next stage in the modulation chain is the randomizing or
“scrambling” stage. Randomizing is necessary due to the fact
that impairments in digital transmission can be a function of the
statistics of the digital source. Receiver symbol synchronization
is more easily maintained if the input sequence appears random
or equiprobable. Long strings of 0s or 1s can cause a bit or
symbol synchronizer to lose synchronization. If there are repeti-
tive patterns in the data, discrete spurs can be produced, caus-
ing interchannel interference. In modulation schemes relying on
suppressed carrier transmission, nonrandom data can increase
the carrier feedthrough. Using a randomizer effectively “whitens”
the data.
The technique used in the AD9853 to randomize the data is to
perform a modulo 2 logic addition of the data with a pseudo-
random sequence. The pseudorandom sequence is generated by
a shift register of length m with an exclusive OR combination of
the nth bit and the last (mth) bit of the shift register that is fed
back to the shift register input. By choosing the appropriate
feedback point, a maximal length sequence is generated. The
maximal length sequence will repeat after every 2m clock cycles,
but appears effectively “random” at the output. The criterion
for maximal length is that the polynomial 1 + xn + xm be irre-
ducible and prime over the Galois field. The AD9853 contains
the following two polynomial configurations in hardware:15 + x14 +1:MCNS (DOCSIS) compatible.6 + x5 +1:DAVIC/DVB compatible.
The seed value is fully programmable for both configurations.
The seed value is reset prior to each burst and is used to calcu-
late the randomizer bit, which is combined in an exclusive XOR
with the first bit of data from each burst. The first bit of data in
a burst is the MSB of the first symbol following the last symbol
PREAMBLE INSERTION BLOCK
As shown in the block diagram of the AD9853, the circuit in-
cludes a programmable preamble insertion register. This register
is 96 bits long and is transmitted upon receiving the TXENABLE
signal. It is transmitted without being Reed-Solomon encoded
or scrambled. Ramp-up data, to allow for receiver synchroniza-
tion, is included as the first bits in the preamble, followed by
user burst profile or channel equalization information. The first
bit of R-S encoded and scrambled information data is timed to
immediately follow the last bit of preamble data.
For most modulation modes, a minimum preamble is required.
This minimum is one symbol, two bits for DQPSK or four bits
for either 16-QAM or D16-QAM. No preamble is required for
either FSK or QPSK.
In conformance with DAVIC/DVB standards, the preamble is
not differentially coded in DQPSK mode. However the pre-
amble data can be differentially precoded when loaded into the
preamble register. The last symbol of the preamble is used as
the reference point for the first internal differentially coded
symbol so the preamble and data will effectively be coded differ-
entially. In the D16-QAM mode, the preamble is always differ-
entially coded internally.
MODULATION ENCODER
The preamble, followed by the encoded and scrambled data is
then modulation encoded according to the selected modulation
format. The available modulation formats are FSK, QPSK,
DQPSK, 16-QAM and D16-QAM. The corresponding symbol
constellations support the interactive HFC cable specifications
called out by MCNS (DOCSIS), 802.14 and DAVIC/DVB.
The data arrives at the modulation encoder at the input bit rate
and is demultiplexed as modulation encoded symbols into sepa-
rate I and Q paths. For QPSK and DQPSK, the symbol rate is
one-half of the bit rate and each symbol is comprised of two
bits. For 16-QAM and D16-QAM, the symbol rate is one-
fourth the bit rate and each symbol is comprised of four bits. In
the FSK mode, although the 1 and 0 data is entered into the
serial data input, it effectively bypasses the encoding, scrambling
and modulation paths. The FSK data is directly routed to the
direct digital synthesizer (DDS) where it is used to switch the
DDS between two stored tuning words (F0:F1) to achieve FSK
modulation in a phase-continuous manner. By holding the input
at either 1 or 0, a single frequency continuous wave can be
output for system test or CW transmission purposes.
Differential encoding of data is frequently used to overcome
phase ambiguity error or a “false lock” condition that can be
introduced in carrier-recovery circuits used to demodulate the
signal. In straight QPSK and 16-QAM, the phase of the re-
ceived signal is compared to that of a “recovered carrier” of
known phase to demodulate the signal in a coherent manner. If
the phase of the recovered carrier is in error, then demodulation
will be in error. Differential encoding of data at the transmit end
eliminates the need for absolute phase coherency of the recov-
ered carrier at the receive end. If a coherent reference generated
by a phase lock loop experiences a phase inversion while de-
modulating in a differentially coded format, the errors would be
limited to the symbol during which the inversion occurred and

Partno	Mfg	Dc	Qty	Available	Descript
AD9853AS	AD	N/a	2	avai	Programmable Digital OPSK/16-QAM Modulator