AD9851BRS Fast Delivery |IC PHOENIX CO.,LIMITED

AD9851BRS ,CMOS 180 MHz DDS/DAC SynthesizerGENERAL DESCRIPTIONThe AD9851 contains an internal high speed comparator thatThe AD9851 is a highly ..
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AD9851BRSZRL ,180 MHz Complete DDS synthesizerCHARACTERISTICS Frequency Range (6 REFCLK Multiplier Disabled) 5.0 V Supply ..
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ADSP-2101-KP-66 ,ADSP-2100 Family DSP MicrocomputersADSP-2100 FamilyaDSP MicrocomputersADSP-21xxFUNCTIONAL BLOCK DIAGRAMSUMMARY16-Bit Fixed-Point DSP M ..
ADSP-2101KP-66 ,ADSP-2100 Family DSP MicrocomputersFeaturesFeature 2101 2103 2105 2115 21111 1Data Memory (RAM) 1K 1K ⁄ K ⁄K1K2 2Program Memory (RAM) ..
ADSP2101-KP-66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2180-Lead PQFP, 80-Lead TQFP . ..
ADSP-2101KP-80 ,ADSP-2100 Family DSP MicrocomputersFeaturesFeature 2101 2103 2105 2115 21111 1Data Memory (RAM) 1K 1K ⁄ K ⁄K1K2 2Program Memory (RAM) ..
ADSP2101-KP80 ,ADSP-2100 Family DSP MicrocomputersSPECIFICATIONSPACKAGE OUTLINE DIMENSIONS(ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . . ..
ADSP-2101-KS-66 ,ADSP-2100 Family DSP MicrocomputersSPECIFICATIONSPACKAGE OUTLINE DIMENSIONS(ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . . ..

AD9851BRS
CMOS 180 MHz DDS/DAC Synthesizer
REV. C
CMOS 180 MHz
DDS/DAC Synthesizer
FUNCTIONAL BLOCK DIAGRAM
FEATURES
180 MHz Clock Rate with Selectable 63 Reference Clock
Multiplier
On-Chip High Performance 10-Bit DAC and High Speed
Comparator with Hysteresis
SFDR >43 dB @ 70 MHz AOUT
32-Bit Frequency Tuning Word
Simplified Control Interface: Parallel or Serial
Asynchronous Loading Format
5-Bit Phase Modulation and Offset Capability
Comparator Jitter <80 ps p-p @ 20 MHz
+2.7 V to +5.25 V Single Supply Operation
Low Power: 555 mW @ 180 MHz
Power-Down Function, 4 mW @ +2.7 V
Ultrasmall 28-Lead SSOP Packaging
APPLICATIONS
Frequency/Phase-Agile Sine Wave Synthesis
Clock Recovery and Locking Circuitry for Digital
Communications
Digitally Controlled ADC Encode Generator
Agile L.O. Applications in Communications
Quadrature Oscillator
CW, AM, FM, FSK, MSK Mode Transmitter
GENERAL DESCRIPTION
The AD9851 is a highly integrated device that uses advanced
DDS technology, coupled with an internal high speed, high
performance D/A converter, and comparator, to form a digitally-
programmable frequency synthesizer and clock generator func-
tion. When referenced to an accurate clock source, the AD9851
generates a stable frequency and phase-programmable digitized
analog output sine wave. This sine wave can be used directly as
a frequency source, or internally converted to a square wave for
agile-clock generator applications. The AD9851’s innovative
high speed DDS core accepts a 32-bit frequency tuning word,
which results in an output tuning resolution of approximately
0.04 Hz with a 180 MHz system clock. The AD9851 contains a
unique 6· REFCLK Multiplier circuit that eliminates the need
for a high speed reference oscillator. The 6· REFCLK Multiplier
has minimal impact on SFDR and phase noise characteristics.
The AD9851 provides five bits of programmable phase modula-
tion resolution to enable phase shifting of its output in incre-
ments of 11.25°.
The AD9851 contains an internal high speed comparator that
can be configured to accept the (externally) filtered output of
the DAC to generate a low jitter output pulse.
The frequency tuning, control and phase modulation words are
asynchronously loaded into the AD9851 via parallel or serial
loading format. The parallel load format consists of five itera-
tive loads of an 8-bit control word (byte). The first 8-bit byte
controls output phase, 6· REFCLK Multiplier, power-down
enable and loading format; the remaining bytes comprise the
32-bit frequency tuning word. Serial loading is accomplished
via a 40-bit serial data stream entering through one of the parallel
input bus lines. The AD9851 uses advanced CMOS technology
to provide this breakthrough level of functionality on just 555 mW
of power dissipation (+5 V supply), at the maximum clock rate of
180 MHz.
The AD9851 is available in a space-saving 28-lead SSOP, sur-
face mount package that is pin-for-pin compatible with the
popular AD9850 125 MHz DDS. It is specified to operate over
the extended industrial temperature range of –40°C to +85°C at
>3.0 V supply voltage. Below 3.0 V, the specifications apply
over the commercial temperature range of 0°C to +85°C.
AD9851–SPECIFICATIONS
(VS1 = +5 V 6 5%, RSET = 3.9 kV, 63 REFCLK Multiplier Disabled, External Reference
Clock = 180 MHz except as noted)
AD9851
CMOS LOGIC INPUTS
NOTES+VS collectively refers to the positive voltages applied to DVDD, PVCC and AVDD. Voltages applied to these pins should be of the same potential.Indicates the minimum signal levels required to reliably clock the device at the indicated supply voltages. This specifies the p-p signal level and dc offset needed when
the clocking signal is not of CMOS/TTL origin, i.e., a sine wave with 0 V dc offset.The comparator’s jitter contribution to any input signal. This is the minimum jitter on the outputs that can be expected from an ideal input. Considerably more
output jitter is seen when nonideal input signals are presented to the comparator inputs. Nonideal characteristics include the presence of extraneous, nonharmonic
signals (spur’s, noise), slower slew rate and low comparator overdrive.Timing of input signals FQ_UD, WCLK, RESET are asynchronous to the Reference Clock; however, the presence of a Reference Clock is required to implement
those functions. In the absence of a Reference Clock, the AD9851 automatically enters power-down mode rendering the IC, including the comparator, inoperable
AD9851
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9851 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Application Note: Users are cautioned not to apply digital input signals prior to power-up of this
device. Doing so may result in a latch-up condition.
ABSOLUTE MAXIMUM RATINGS*
Maximum Junction Temperature . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6 V
Operating Temperature . . . . . . . . . . . . . . . . .–40°C to +85°C
Digital Inputs . . . . . . . . . . . . . . . . . . .–0.7 V to +VS + 0.7 V
Lead Temperature (10 sec) Soldering . . . . . . . . . . . . .+300°C
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . .30 mA
SSOP qJA Thermal Impedance . . . . . . . . . . . . . . . . . .82°C/W
DAC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . .30 mA
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
EXPLANATION OF TEST LEVELS
Test Level–100% Production Tested.
III–Sample Tested Only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–Devices are 100% production tested at +25°C and
guaranteed by design and characterization testing for
industrial operating temperature range.
ORDERING GUIDE
PIN FUNCTION DESCRIPTIONS
10, 19
11, 18
PIN CONFIGURATION
VOUTN
RSET
AVDD
AGND
REFCLOCKUD
LSB D0
PVCC
PGND
VINP
DACBP
AVDD
AGND
IOUTB
IOUT
D7 MSB/SERIAL LOAD
RESET
DVDD
DGNDCLK
AD9851
Both IOUT and IOUTB are equally loaded with 100 W. Two
100 kW resistors “sample” each output and average the two
voltages. The result is filtered with the 470 pF capacitor and
applied to one comparator input as a dc switching threshold.
The filtered DAC sine wave output is applied to the other com-
parator input. The comparator will toggle with nearly 50% duty
cycle as the sine wave alternately traverses the “center point”
threshold.
REFERENCE
CLOCK
IF FREQUENCY
IN
TUNING
WORD
FREQUENCY
OUT
Figure 3. Frequency/Phase-Agile Local Oscillator for
Frequency Mixing/Multiplying
REFERENCE
CLOCK
TUNING
WORD
FREQUENCY
OUT
ADC ENCODE
AGC
CHIP/SYMBOL/PN
RATE DATA
ADC CLOCK FREQUENCY
LOCKED TO
Tx CHIP/SYMBOL/PN RATE
180MHz
OR 30MHz
REFERENCE
CLOCK
Rx BASEBAND
DIGITAL DATA OUT
RF IN
VCA
Figure 1.“Chip Rate” Clock Generator Application in a Spread Spectrum Receiver
3.9kV
Figure 2.Basic Clock Generator Configuration
Figure 5.Digitally-Programmable “Divide-by-N” Function
in PLL
Figure 6.High Quality, All-Digital RF Frequency Modulation
High quality, all digital RF frequency modulation generation
with the ADSP-2181 DSP and the AD9851 DDS. This applica-
tion is well documented in Analog Devices’ application Note
AN-543, and uses an “image” of the DDS output as illustrated
in Figure 8.
PHASE
DIFFERENCECLK #2CLK #1
Figure 7.Application Showing Synchronization of Two
AD9851 DDSs to Form a Quadrature Oscillator
After a common RESET command is issued, separate W_CLKs
allow independent programming of each AD9851 40-bit input
register via the 8-bit data bus or serial input pin. A common
FQ_UD pulse is issued after programming is completed to
simultaneously engage both oscillators at their specified fre-
quency and phase.
30MHz
CLOCK
BANDPASS
AMPLITUDE120180240
FREQUENCY – MHz
FREQUENCY – MHz
AMPLITUDE
AMPLIFIER
AD9851
SPECTRUM
FINAL OUTPUT
SPECTRUM
Figure 8.Deriving a High Frequency Output Signal from
the AD9851 by Using an “Alias” or Image Signal
Differential DAC output connection (Figure 9) for reduction of
common-mode signals and to allow highly reactive filters to be
driven without a filter input termination resistor (see above
single-ended example, Figure 8). A 6 dB power advantage is
obtained at the filter output as compared with the single-ended
example, since the filter need not be doubly terminated.
Figure 9.Differential DAC Output Connection for Reduc-
tion of Common-Mode Signals
The AD9851 RSET input being driven by an external DAC
(Figure 10) to provide amplitude modulation or fixed, digital
amplitude control of the DAC output current. Full description
of this application is found as a “Technical Note” on the AD9851
web page (site address is ) under “Related
Information.” An Analog Devices application note for the
AD9850, AN-423, describes another method of amplitude
control using an enhancement-mode MOSFET that is equally
applicable to the AD9851.
NOTE: If the 6· REFCLK Multiplier of the AD9851 is en-
gaged, the 125 MHz clocking source shown in Figure 10 can be
reduced by a factor of six.
DIFFERENTIAL
1:1 TRANSFORMER
+5V
+5V
+5V
Figure 10.The AD9851 RSET Input Being Driven by an External DAC
AD9851
THEORY OF OPERATION AND APPLICATION
The AD9851 uses direct digital synthesis (DDS) technology, in
the form of a numerically-controlled oscillator (NCO), to gen-
erate a frequency/phase-agile sine wave. The digital sine wave is
converted to analog form via an internal 10-bit high speed D/A
converter. An on-board high-speed comparator is provided to
translate the analog sine wave into a low-jitter TTL/CMOS-
compatible output square wave. DDS technology is an innova-
tive circuit architecture that allows fast and precise manipulation
of its output word, under full digital control. DDS also enables
very high resolution in the incremental selection of output fre-
quency. The AD9851 allows an output frequency resolution of
approximately 0.04 Hz at 180 MSPS clock rate with the option of
directly using the reference clock or by engaging the 6· REFCLK
Multiplier. The AD9851’s output waveform is phase-continu-
ous from one output frequency change to another.
The basic functional block diagram and signal flow of the
AD9851 configured as a clock generator is shown in Figure 11.
The DDS circuitry is basically a digital frequency divider func-
tion whose incremental resolution is determined by the frequency
of the system clock, and N (number of bits in the tuning word).
The phase accumulator is a variable-modulus counter that
increments the number stored in it each time it receives a clock
pulse. When the counter reaches full scale it “wraps around,”
making the phase accumulator’s output phase-continuous. The
frequency tuning word sets the modulus of the counter, which
effectively determines the size of the increment (D Phase) that
will be added to the value in the phase accumulator on the next
clock pulse. The larger the added increment, the faster the
accumulator wraps around, which results in a higher output
frequency.
The AD9851 uses an innovative and proprietary “Angle
Rotation” algorithm that mathematically converts the 14-bit
truncated value of the 32-bit phase accumulator to the 10-bit
quantized amplitude that is passed to the DAC. This unique
algorithm uses a much-reduced ROM look-up table and DSP to
perform this function. This contributes to the small size and
low power dissipation of the AD9851.
The relationship between the output frequency, system clock
and tuning word of the AD9851 is determined by the expression:
fOUT = (D Phase · System Clock)/232
where:Phase = decimal value of 32-bit frequency tuning word.
System Clock = direct input reference clock (in MHz) or 6· the
input clock (in MHz) if the 6· REFCLK Multiplier is engaged.
fOUT = frequency of the output signal in MHz.
The digital sine wave output of the DDS core drives the internal
high-speed 10-bit D/A converter that will construct the sine
wave in analog form. This DAC has been optimized for dynamic
performance and low glitch energy, which results in the low
spurious and jitter performance of the AD9851. The DAC can
be operated in either the single-ended, Figures 2 and 8, or dif-
ferential output configuration, Figures 9 and 10. DAC output
current and RSET values are determined using the following
expressions:
IOUT = 39.93/RSET
RSET = 39.93/IOUT
Since the output of the AD9851 is a sampled signal, its output
spectrum follows the Nyquist sampling theorem. Specifically, its
output spectrum contains the fundamental plus aliased signals
(images) that occur at integer multiples of the system clock
frequency – the selected output frequency. A graphical repre-
sentation of the sampled spectrum, with aliased images, is shown in
Figure 12. Normal usable bandwidth is considered to extend
from dc to 1/2 the system clock.
In the example shown in Figure 12, the system clock is 100 MHz
and the output frequency is set to 20 MHz. As can be seen, the
aliased images are very prominent and of a relatively high energy
CLOCK
OUT
TUNING WORD SPECIFIES
OUTPUT FREQUENCY AS A
FRACTION OF REF CLOCK
FREQUENCY
DOMAIN
Figure 11.Basic DDS Block Diagram and Signal Flow of AD9851
120MHz
180MHz
220MHz
280MHz
80MHz
20MHz0Hz
SIGNAL AMPLITUDE
level as determined by the sin(x)/x roll-off of the quantized D/A
converter output. In fact, depending on the f/system clock rela-
tionship, the 1st aliased image can equal the fundamental
amplitude (when fOUT = 1/2 system clock). A low-pass filter is
generally placed between the output of the D/A converter and
the input of the comparator to suppress the jitter-producing
effects of non-harmonically related aliased images and other
spurious signals. Consideration must be given to the relationship
of the selected output frequency, the system clock frequency and
alias frequencies to avoid unwanted output anomalies.
Images need not be thought of as useless by-products of a DAC.
In fact, with bandpass filtering around an image and some
amount of post-filter amplification, the image can become the
primary output signal (see Figure 8). Since images are not har-
monics, they retain a 1:1 Dfrequency relationship to the funda-
mental output. That is, if the fundamental is shifted 1 kHz, then
the image is also shifted 1 kHz. This relationship accounts for
the frequency stability of an image, which is identical to that of
the fundamental. Users should recognize that the lower image of
an image pair surrounding an integer multiple of the system clock
will move in a direction opposite the fundamental. Images of an
image pair located above an integer multiple of the system clock
will move in the same direction as a fundamental movement.
The frequency band where images exist is much richer in spuri-
ous signals and therefore, more hostile in terms of SFDR. Users
of this technique should empirically determine what frequencies
are usable if their SFDR requirements are demanding.
A good “rule-of-thumb” for applying the AD9851 as a clock
generator is to limit the fundamental output frequency to 40% of
Reference Clock frequency to avoid generating aliased signals
that are too close to the output band of interest (generally dc—
highest selected output frequency) to be filtered. This practice
will ease the complexity and cost of the external filter require-
ment for the clock generator application.
The reference clock input of the AD9851 has minimum limita-
tion of 1 MHz without 6· REFCLK Multiplier engaged and
5 MHz with multiplier engaged. The device has internal cir-
cuitry that senses when the clock rate has dropped below the
minimum and automatically places itself in the power-down
mode. In this mode, the on-chip comparator is also disabled.
This is important information for those who may wish to use the
on-chip comparator for purposes other than squaring the DDS
sine wave output. When the clock frequency returns above the
minimum threshold, the device resumes normal operation after
5 ms (typically). This shutdown mode prevents excessive current
leakage in the dynamic registers of the device.
The impact of reference clock phase noise in DDS systems is
actually reduced, since the DDS output is the result of a division
of the input frequency. The amount of apparent phase noise
reduction, expressed in dB, is found using: 20 log fOUT/fCLK.
Where fOUT is the fundamental DDS output frequency and fCLK
is the system clock frequency. From this standpoint, using the
highest system clock input frequency makes good sense in reduc-
ing the effects of reference clock phase noise contribution to the
output signals’ overall phase noise. As an example, an oscilla-
tor with –100 dBc phase noise operating at 180 MHz would
increase is due to the inherent 6· (15.5 dB) phase gain transfer
function of the 6· REFCLK Multiplier, as well as noise gener-
ated internally by the clock multiplier circuit. By using a low
phase noise reference clock input to the AD9851, users can be
assured of better than –100 dBc/Hz phase noise performance
for output frequencies up to 50 MHz at offsets from 1 kHz to
100 kHz.
Programming the AD9851
The AD9851 contains a 40-bit register that stores the 32-bit
frequency control word, the 5-bit phase modulation word, REFCLK Multiplier enable and the power-down function.
This register can be loaded in parallel or serial mode. A logic
high engages functions; for example, to power-down the IC
(sleep mode), a logic high must be programmed in that bit
location. Those users who are familiar with the AD9850 DDS
will find only a slight change in programming the AD9851,
specifically, data[0] of W0 (parallel load) and W32 (serial load)
now contains a “6· REFCLK Multiplier Enable” bit that needs
to be set high to enable or low to disable the internal reference
clock multiplier.
Note: setting “data[1]” high in programming word W0 (paral-
lel mode) or word W33 high in serial mode is not allowed (see
Tables I and III). This bit controls a “factory test mode” that
will cause abnormal operation in the AD9851 if set high. If
erroneously entered (as evidenced by Pin 2 changing from an
input pin to an output signal), an exit is provided by asserting
RESET. Unintentional entry to the factory test mode can
occur if an FQ_UD pulse is sent after initial power-up and
RESET of the AD9851. Since RESET does not clear the 40-
bit input register, this will transfer the random power-up values
of the input register to the DDS core. The random values may
invoke the factory test mode or power-down mode. Never issue
an FQ_UD command if the 40-bit input register contents are
unknown.
In the default parallel load mode, the 40-bit input register is
loaded using an 8-bit bus. W_CLK is used to load the register
in five iterations of eight bytes. The rising edge of FQ_UD
transfers the contents of the register into the device to be acted
upon and resets the word address pointer to W0. Subsequent
W_CLK rising edges load 8-bit data, starting at W0 and then
move the word pointer to the next word. After W0 through W4
are loaded, additional W_CLK edges are ignored until either a
RESET is asserted or an FQ_UD rising edge resets the address
pointer to W0 in preparation for the next 8-bit load. See Fig-
ure 13.
In serial load mode, forty subsequent rising edges of W_CLK
will shift and load the 1-bit data on Pin 25 (D7) through the
40-bit register in “shift-register” fashion. Any further W_CLK
rising edges after the register is full will shift data out causing
data that is left in the register to be out-of-sequence and cor-
rupted. The serial mode must be entered from the default
parallel mode, see Figure 17. Data is loaded beginning with
W0 and ending with W39. One note of caution: the 8-bit
parallel word (W0)—xxxxx011—that invokes the serial mode
should be overwritten with a valid 40-bit serial word immedi-
ately after entering the serial mode to prevent unintended
AD9851
Table I.8-Bit Parallel-Load Data/Control Word Functional Assignment
*This bit is always Logic 0 unless invoking the serial mode (see Figure 17). After serial mode is entered, this data bit must be set back to Logic 0 for proper operation.
SYSCLK
DATACLK
Note: To update W0 it is not necessary to load W1 through W4. Simply load W0 and assert FQ_UD. To update W1, reload W0
then W1...users do not have random access to programming words.
The function assignments of the data and control words are
shown in Tables I and III; the detailed timing sequence for
updating the output frequency and/or phase, resetting the de-
vice, engaging the 6· REFCLK Multiplier, and powering up/
down, are shown in the timing diagrams of Figures 13–20. As a
programming example for the following DDS characteristics:Phase set to 11.25 degrees.6· REFCLK Multiplier engaged.Powered-up mode selected.Output = 10 MHz (for 180 MHz system clock).
In parallel mode, user would program the 40-bit control word
(composed of five 8-bit loads) as follows:
W0 = 00001001
W1 = 00001110
W2 = 00111000
W3 = 11100011
W4 = 10001110
If in serial mode, load the 40 bits starting from the LSB location
of W4 in the above “array,” loading from right to left, and end-
ing with the MSB of W0.
Results of Reset, Figure 14Phase Accumulator zeroed such that the output = 0 Hertz
(dc).Phase Offset register set to zero such that DAC IOUT = Full-
Scale output and IOUTB = zero mA output.Internal Programming Address pointer reset to W0.Power-down bit reset to “0” (power-down disabled).40-bit Data Input Register is NOT cleared.
–6· Reference Clock multiplier is disabled.Parallel programming mode selected by default.UDCLK
SYSCLK
DAC
STROBE
DATA (W0)
DISABLED
Figure 15.
Operation
DATA (W0)
INTERNAL CLOCKS
ENABLED
SYSCLK
Figure 16.Parallel-Load Power-Up Sequence (to Recover
from Power-Down)/Internal Operation
which is selected by default after a RESET is asserted. One
needs only to program the first eight bits (word W0) with the
sequence xxxxx011 as shown in Figure 17 to change from paral-
lel to serial mode. The W0 programming word may be sent over
the 8-bit data bus or hardwired as shown in Figure 18. After
serial mode is achieved, the user must follow the programming
sequence of Figure 19.
Figure 17.Serial-Load Enable Sequence
Note: After serial mode is invoked, it is best to immediately
write a valid 40-bit serial word (see Figure 19), even if it is all
zeros, followed by a FQ_UD rising edge to flush the “residual”
data left in the DDS core. A valid 40-bit serial word is any word
where W33 is Logic 0.+V
SUPPLY
Figure 18.Hardwired xxxxx011 Configuration for Serial-
Load Enable Word W0 in Figure 17
AD9851DATA
Figure 19.Serial-Load Frequency/Phase Update Sequence
Table III.40-Bit Serial-Load Word Functional Assignment
W27
W28
W29
W30
W31
W32
W33
W34
W35
W36
W37
W38
W39
*This bit is always Logic 0.DATA (7) –
Figure 20.Serial-Load Power-Down\Power-Up Sequence
DIGITAL
OUT
VDD
IOUTIOUTB
VDD
VINP/
VINN
VDD
DIGITAL
VDDDAC Output b.Comparator Output c.Comparator Input d.Digital Input
Figure 21.I/O Equivalent Circuits
Figure 20 shows a normal 40-bit serial word load sequence with
W33 always set to Logic 0 and W34 set to Logic 1 or Logic 0 to
control the power-down function. The logic states of the remain-
ing 38 bits are unimportant and are marked with an X, indicating
“don’t care” status. To power down, set W34 = 1. To power up
from a powered down state, change W34 to Logic 0. Wake-up
from power-down mode requires approximately 5 ms.
Note: The 40-bit input register of the AD9851 is fully program-
mable while in the power-down mode.

Partno	Mfg	Dc	Qty	Available	Descript
AD9851BRS	ADI	N/a	553	avai	CMOS 180 MHz DDS/DAC Synthesizer