AD9842AJST ,Complete 20 MSPS CCD Signal Processorsfeatures include gain adjustment,Digital Still Camerasblack level adjustment, input configuration, a ..
AD9842AJSTRL ,Complete 12-Bit, 20 MHz CCD Signal Processor with PxGA™SPECIFICATIONS wise noted.)Parameter Min Typ Max Unit NotesPOWER CONSUMPTION 78 mW See TPC 1 for Po ..
AD9843A ,Complete 10-Bit, 20 MHz CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotesPOWER CONSUMPTION 78 mW See TP ..
AD9843AJST ,Complete 10-Bit 20 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotesPOWER CONSUMPTION 78 mW See TP ..
AD9843AJSTRL ,Complete 10-Bit, 20 MHz CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotesPOWER CONSUMPTION 78 mW See TP ..
AD9843AJSTZ ,Complete 10-Bit, 20 MHz CCD Signal ProcessorAPPLICATIONSDigital Still CamerasThe AD9843A operates from a single 3 V power supply, typi-Digital ..
ADSP-2100AJG ,12.5 MIPS DSP Microprocessorspecifications differ as shown in those sections of the data sheet.
Both processors integrate co ..
ADSP-2101BP-100 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2180-Lead PQFP, 80-Lead TQFP . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersFEATURES(ADSP-2111)25 MIPS, 40 ns Maximum Instruction Rate ADSP-2100 CORE Separate On-Chip Buses fo ..
ADSP-2101BS-100 ,ADSP-2100 Family DSP Microcomputersfeatures plus 80K bytes of on-chip RAMand, on the ADSP-2111, a host interface port.configured as 16 ..
ADSP-2101BS-66 ,ADSP-2100 Family DSP MicrocomputersADSP-2100 FamilyaDSP MicrocomputersADSP-21xxFUNCTIONAL BLOCK DIAGRAMSUMMARY16-Bit Fixed-Point DSP M ..
AD9841AJST-AD9842AJST
Complete 20 MSPS CCD Signal Processors
REV.0
Complete 20 MSPS
CCD Signal Processors
FUNCTIONAL BLOCK DIAGRAM
DATACLKSHDSHPDOUT
AUX2IN
CLPDM
CCDIN
PBLK
AUX1IN
VRT
VRB
AVDD
DVDD
DVSS
AVSS
DRVDD
DRVSS
CML
SDATASCKSL
CLPOBVD
FEATURES
20 MSPS Correlated Double Sampler (CDS)
4 dB � 6 dB 6-Bit Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit (9841) or 12-Bit (9842) 20 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 65 mW @ 2.7 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
PRODUCT DESCRIPTIONThe AD9841A and AD9842A are complete analog signal proces-
sors for CCD applications. Both products feature a 20MHz
single-channel architecture designed to sample and condition
the outputs of interlaced and progressive scan area CCD arrays.
The AD9841A/AD9842A’s signal chain consists of an input
clamp, correlated double sampler (CDS), Pixel Gain Amplifier
(PxGA), digitally controlled variable gain amplifier (VGA),
black level clamp, and A/D converter. The AD9841A offers 10-bit
ADC resolution, while the AD9842A contains a true 12-bit
ADC. Additional input modes are provided for processing analog
video signals.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment,
black level adjustment, input configuration, and power-down modes.
The AD9841A and AD9842A operate from a single 3 V power
supply, typically dissipate 78 mW, and are packaged in a 48-
lead LQFP.
PxGA is a registered trademark of Analog Devices, Inc.
AD9841A/AD9842A–SPECIFICATIONS
GENERAL SPECIFICATIONSPOWER SUPPLY VOLTAGE
Specifications subject to change without notice.
DIGITAL SPECIFICATIONSLOGIC OUTPUTS
Specifications subject to change without notice.
(DRVDD = 2.7 V, CL = 20 pF unless otherwise noted.)
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
AD9841A/AD9842APIXEL GAIN AMPLIFIER (PxGA)
VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
SYSTEM PERFORMANCE
NOTESInput Signal Characteristics defined as follows:PxGA gain fixed at 4 dB.
Specifications subject to change without notice.
AD9841A CCD-MODE SPECIFICATIONS
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 20 MHz, unless other-
wise noted.)
AD9841A/AD9842A–SPECIFICATIONSPIXEL GAIN AMPLIFIER (PxGA)
VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
SYSTEM PERFORMANCE
NOTESInput Signal Characteristics defined as follows:PxGA gain fixed at 4 dB.
Specifications subject to change without notice.
AD9842A CCD-MODE SPECIFICATIONS
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 20 MHz, unless
otherwise noted)
AD9841A/AD9842A
AUX1-MODE SPECIFICATIONSSpecifications subject to change without notice.
AUX2-MODE SPECIFICATIONSACTIVE CLAMP (AD9841A)
ACTIVE CLAMP (AD9842A)
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
AD9841A/AD9842A
TIMING SPECIFICATIONSSERIAL INTERFACE
NOTESMinimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9841A/AD9842A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
(CL = 20 pF, fSAMP = 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 21–24.)
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
THERMAL CHARACTERISTICS
Thermal Resistance48-Lead LQFP Package
θJA = 92°C
PIN FUNCTION DESCRIPTIONS
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
CCDIN
(LSB) D0
NC = NO CONNECT
BYP2
BYP1
AVDD1
AVSS
(MSB) D9AVSS
SCKSDATASLNCSTBYNCTHREE-
STATE
DVSSDVDD2VRBVRTCML
DRVDDDRVSS
DVSS
DATACLK
DVDD1
PBLK
CLPOB
SHP
SHD
CLPDM
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
CCDIN
(LSB) D0
NC = NO CONNECT
D10
BYP2
BYP1
AVDD1
AVSS
(MSB) D11AVSS
SCKSDATASLNCSTBYNCTHREE-STATEDVSSDVDD2VRBVRTCML
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
PBLK
CLPOB
SHPSHD
CLPDM
PIN CONFIGURATIONS
AD9841A/AD9842A
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 12-bit
resolution indicates that all 4096 codes, respectively, must be
present over all operating conditions.
PEAK NONLINEARITYPeak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD984x from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level 1,
1/2 LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the true straight
line. The error is then expressed as a percentage of the 2 V ADC
full-scale signal. The input signal is always appropriately gained up
to fill the ADC’s full-scale range.
TOTAL OUTPUT NOISEThe rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2N codes) when N is the bit resolution of the
ADC. For the AD9842A, 1 LSB is 500 µV, and for the AD9841A,
1 LSB is 2 mV.
POWER SUPPLY REJECTION (PSR)The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD984xA’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
INTERNAL DELAY FOR SHP/SHDThe internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD984xA
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITSFigure 1.Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
DVDD
DRVDD
THREE-
STATE
DATA
DOUTFigure 3.CCDIN (Pin 30)
SAMPLE RATE – MHz
POWER DISSIPATION
mWTPC 1.AD9841A/AD9842A Power vs. Sample Rate
TPC 2.AD9841A Typical DNL Performance
TPC 3.AD9841A Output Noise vs. VGA Gain
TPC 4.AD9842A Typical DNL Performance
TPC 5.AD9842A Output Noise vs. VGA Gain
AD9841A/AD9842A
CCD-MODE AND AUX MODE TIMINGFigure 5.CCD-Mode Timing
CCD
SIGNAL
EFFECTIVE PIXELS
CLPOB
CLPDM
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKINGDUMMY PIXELSEFFECTIVE PIXELS
PBLK
NOTES:
1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
OUTPUT
DATAFigure 6.Typical CCD-Mode Line Clamp Timing
PIXEL GAIN AMPLIFIER (PxGA) TIMINGFigure 8.PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence
Figure 9.PxGA Mode 1 (Mosaic Separate) Detailed Timing
Figure 10.PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence
AD9841A/AD9842AFigure 12.PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence
Figure 13.PxGA Mode 3 (3-Color) Detailed Timing
Figure 14.PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence
