AD9802JST Fast Delivery |IC PHOENIX CO.,LIMITED

AD9802JST ,CCD Signal Processor For Electronic CamerasSPECIFICATIONSnoted)Parameter Min Typ Max UnitsADCCLK Clock Period 55.6 nsADCCLK Hi-Level Period 24 ..
AD9802JST ,CCD Signal Processor For Electronic Camerasapplications. allow for simple ac-coupling to interface a CCD sensor at full18 MSPS conversion rate ..
AD9803JST ,CCD Signal Processor For Electronic CamerasSPECIFICATIONS (T to T , ACVDD = ADVDD = DVDD = +2.8 V, f = 18 MHz unless otherwise noted)MIN MAX A ..
AD9804AJST ,Complete 10-Bit, 18 MHz CCD Signal ProcessorSPECIFICATIONS L CLKParameter Symbol Min Typ Max UnitSAMPLE CLOCKSDATACLK, SHP, SHD Clock Period t ..
AD9804JST ,Complete 10-Bit 18 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHD Parameter Min Typ Max UnitTEMPERATURE RANGEOperating –20 +85 ..
AD9805JS ,Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal ProcessorsSPECIFICATIONSPGA Gain = 1 unless otherwise noted)Parameter Min Typ Max UnitsRESOLUTION 12 BitsCON ..
ADS8517IDW ,Low Power 16-Bit, 200kSPS, +/-10V Bipolar Input SAR ADC with S/P Interface 28-SOIC -40 to 85Maximum Ratings may cause permanent damage to the device. Exposure to absolutemaximum conditions fo ..
ADS8517IPW ,Low Power 16-Bit, 200kSPS, +/-10V Bipolar Input SAR ADC with S/P Interface 28-TSSOP -40 to 85ELECTRICAL CHARACTERISTICSAt T = -40°C to +85°C, f = 200 kHz, V = V = 5 V, using internal reference ..
ADS8517IPWR ,Low Power 16-Bit, 200kSPS, +/-10V Bipolar Input SAR ADC with S/P Interface 28-TSSOP -40 to 85.(1)(2)ABSOLUTE
ADS8519IB , 16-Bit, 250kSPS, Serial, CMOS, Sampling ANALOG-TO-DIGITAL CONVERTER
ADS8519IBDB ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Serial Interface 4.096V Internal Reference 28-SSOP -40 to 85This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
ADS8519IBDBG4 ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Serial Interface 4.096V Internal Reference 28-SSOP -40 to 85FEATURES DESCRIPTION23• 0V to 8.192V, ±5V, and ±10V Input RangesThe ADS8519 is a complete 16-bit sa ..

AD9802JST
CCD Signal Processor For Electronic Cameras
REV.0
CCD Signal Processor
For Electronic Cameras
FUNCTIONAL BLOCK DIAGRAM
SHP
PGACONT1 PGACONT2
CLPDMPBLK
PIN
DIN
SHDADCCLK
CMLEVELVRTVRBSTBY
CLPOB
DOUTADCIN
ADCMODE
DRVDD
DVDD
ADVDDACVDD
FEATURES
10-Bit, 18 MSPS A/D Converter
18 MSPS Full Speed Correlated Double Sampler (CDS)
Low Noise, Wideband PGA
Internal Voltage Reference
No Missing Codes Guaranteed
+3 V Single Supply Operation
Low Power CMOS:185 mW
48-Terminal TQFP Package
PRODUCT HIGHLIGHTSOn-Chip Input Clamp and CDS
Clamp circuitry and high speed correlated double sampler
allow for simple ac-coupling to interface a CCD sensor at full
18 MSPS conversion rate.On-Chip PGA
The AD9802 includes a low-noise, wideband amplifier with
analog variable gain from 0 dB to 31.5 dB (linear in dB).Direct ADC Input
A direct input to the 10-bit A/D converter is provided for
digitizing video signals.10-Bit, High Speed A/D Converter
A linear 10-bit ADC is capable of digitizing CCD signals at
the full 18 MSPS conversion rate. Typical DNL is ±0.5LSB
and no missing code performance is guaranteed.Low Power
At 185 mW, and 15 mW in power-down, the AD9802 con-
sumes a fraction of the power of presently available multichip
solutions.Digital I/O Functionality
The AD9802 offers three-state digital output control.Small Package
Packaged in a 48-terminal, surface-mount thin quad flatpack,
the AD9802 is well suited to very compact, low headroom
designs.
PRODUCT DESCRIPTION
The AD9802 is a complete CCD signal processor developed
for electronic cameras. It is suitable for both camcorder and
consumer-level still camera applications.
The signal processing chain is comprised of a high speed CDS,
variable gain PGA and 10-bit ADC. Required clamping cir-
cuitry and an onboard voltage reference are provided as well as a
direct ADC input. The AD9802 operates from a single +3V
supply with a typical power consumption of 185mW.
The AD9802 is packaged in a space saving 48-terminal thin
quad flatpack (TQFP) and is specified over an operating tem-
perature range of 0°C to +70°C.
AD9802–SPECIFICATIONS
(TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V
unless otherwise noted)
POWER SUPPLY VOLTAGE (For Functional Operation)
POWER SUPPLY CURRENT
POWER CONSUMPTION
CDS
PGA
CLAMP (During CLPOB. Only Stable over PGA Range 0.3 V to 2.7 V)
NOTESPGA test conditions:maximum gain PGACONT1 = 2.7 V, PGACONT2 = 1.5 V; high gain PGACONT1 = 2.0 V, PGACONT2 = 1.5 V; medium gain PGACONT1 =
0.5 V, PGACONT2 = 1.5 V; minimum gain PGACONT1 = 0.3 V, PGACONT2 = 1.5 V.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise
noted)
TIMING SPECIFICATIONS
Digital Output Data Control
(TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise
noted)
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods
may affect device reliability.
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
AD9802
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
DVDD
DSUBST
DVSS
ADCCLK
STBY
ADVSS
(LSB) D0
(MSB) D9
DRVDD
NC = NO CONNECT
PBLK
CLPOB
SHPSHD
DVSS
ADCIN
TEST2
TEST1
ACVDD
CLAMP_BIAS
ACVSS
PGACONT2
PGACONT1
CCDBYP1
PIN
DIN
CCDBYP2
VRT
VRBSUBST
ADVSS
ADVSS
ADVDD
ADCMODE
MODE1MODE2
SHABYP
CMLEVEL
CLPDM
DRVSS
EQUIVALENT INPUT CIRCUITS
DVDDDRVDD
DVSSDRVSS
Figure 1.Pins 2–11 (DB0–DB9)
DVDD
DSUBSTDVSS
Figure 2.Pin 21 (SHP) and Pin 22 (SHD)
DVDD
DSUBSTDVSS
Figure 3.Pin 16 (ADCCLK)
ADVDD
ADVSS
9.3kV
Figure 4.Pin 37 (CMLEVEL)
ACVDD
SUBST
ACVSS
10pF
Figure 6.Pin 26 (DIN) and Pin 27 (PIN)
ACVDD
ACVDD
PGACONT1
PGACONT2
Figure 7.Pin 29 (PGACONT1) and Pin 30 (PGACONT2)
ACVDD
SUBSTACVSS
Figure 8.Pin 32 (CLAMP BIAS)
Figure 9.Pin 48 (VRT) and Pin 47 (VRB)
ACVDD
SUBST
1pF
Figure 10.Pin 36 (ADCIN) and Pin 38 (SHABYP)
AD9802
EFFECTIVE
PIXEL
INTERVAL
BLACK
LEVEL
INTERVAL
BLANKING
INTERVAL
DUMMY
BLACK
INTERVAL
EFFECTIVE
PIXEL
INTERVAL
CCD
SHP
SHD
CLPOB
PBLK
CLPDM
ADCCLK
ADC DATA
NOTES:
CLPDM AND CLPOB OVERWRITE PBLK
CLAMP TIMING NEEDS TO BE ADJUSTED RELATIVE TO CCD'S BLACK PIXELS
RECOMMENDED PULSE WIDTH CLPDM = 1.5s MIN
Figure 11.Typical Horizontal Interval Timing
CCD SIGNAL
(DELAYED TO MATCH
ACTUAL SAMPLING
EDGE)
SHD
SHP
ACTUAL
SAMPLING
EDGE
ADCCLK
DIGITAL OUT
OUTPUT LOAD CL = 20pF OUTPUT DELAY tOD = 15ns
LATENCY = 5 CYCLES
INTERNAL CLOCK DELAY tID = 3ns
HOLD TIME tH = 2ns
Figure 12.Timing Diagram
SHP
SHD
ADCCLKINHIBITED PERIOD
FOR ADCCLK
RISING EDGE
PRE-ADC
OUTPUT LATCH
PRE-ADC
OUTPUT LATCH
DATA TRANSITION
Figure 13.ADCCLK Timing Edge
AD9802
THEORY OF OPERATION
Introduction
The AD9802 is a 10-bit analog-to-digital interface for CCD
cameras. The block level diagram of the system is shown in
Figure 14. The device includes a correlated double sampler
(CDS), 0dB–31 dB variable gain amplifier (PGA), black level
correction loop, input clamp and voltage reference. The only
external analog circuitry required at the system level is an emit-
ter follower buffer between the CCD output and AD9802
inputs.
OUT
GAIN
Figure 14.
Correlated Double Sampling (CDS)
CDS is important in high performance CCD systems as a method
for removing several types of noise. Basically, two samples of the
CCD output are taken: one with the signal present (data) and one
without (reference). Subtracting these two samples removes
any noise that is common to—or correlates with—both.
Figure 15 shows the block diagram of the AD9802’s CDS. The
S/H blocks are directly driven by the input and the sampling
function is performed passively, without the use of amplifiers.
This implementation relies on the off-chip emitter follower
buffer to drive the two 10pF sampling capacitors. Only one
capacitor at a time is seen at the input pin.
The AD9802 actually uses two CDS circuits in a “ping-pong”
fashion to allow the system more acquisition time. In this way,
the output from one of the two CDS blocks will be valid for an
entire clock cycle. Thus, the bandwidth requirement of the
subsequent gain stage is reduced as compared to that for a
single CDS channel system. This lower bandwidth translates to
lower power and noise.OUTFROM
CCD
Figure 15.
Programmable Gain Amplifier (PGA)
The on-chip PGA provides a (linear in dB) gain range of 0dB–
31.5 dB. A typical gain characteristic plot is shown in Figure 16.
Only the range from 0.3 V to 2.7 V is intended for actual use.
GAIN – dB
PGACONT1 – Volts
–10
Figure 16.
As shown in Figure 17, PGA control is provided through the
PGACONT1 and PGACONT2 inputs. PGACONT1 provides
coarse, and PGACONT2 fine (1/16), gain control.
PGACONT1PGACONT2
PGACONT1 = COARSE CONTROL
PGACONT2 = FINE (1/16) CONTROL
Figure 17.
Black Level Clamping
For correct processing, the CCD signal must be referenced to a
well established “black level” by the AD9802. At the edge of the
CCD, there is a collection of pixels covered with metal to pre-
vent any light penetration. As the CCD is read out, these “black
pixels” provide a calibration signal that is used to establish the
black level.
The feedback loop shown in Figure 18 is closed around the
PGA during the calibration interval (CLPOB = LOW) to set the
black level. As the black pixels are being processed, an integra-
tor block measures the difference between the input level and
the desired reference level. This difference, or error, signal is
amplified and passed to the CDS block where it is added to the
incoming pixel data. As a result of this process, the black pixels
are digitized at one end of the ADC range, taking maximum
advantage of the available linear range of the system.ADCIN
CLPOB
NEG REF
Figure 18.
The actual implementation of this loop is slightly more compli-
cated as shown in Figure 19. Because there are two separate
CDS blocks, two black level feedback loops are required and
two offset voltages are developed. Figure 19 also shows an addi-
tional PGA block in the feedback loop labeled “RPGA.” The
RPGA uses the same control inputs as the PGA, but has the
inverse gain. The RPGA functions to attenuate by the same
factor as the PGA amplifies, keeping the gain and bandwidth of
the loop constant.
There exists an unavoidable mismatch in the two offset voltages
used to correct both CDS blocks. This mismatch causes a slight
difference in the offset level for odd and even pixels, called
“pixel-to-pixel offset” (see Specifications). The pixel-to-pixel
offset is an output referred specification, because the black level
correction is done using the output of the PGA.ADCIN
CLPOB
NEG REF
Figure 19.
Input Bias Level Clamping
The buffered CCD output is connected to the AD9802 through
an external coupling capacitor. The dc bias point for this cou-
pling capacitor is established during the clamping (CLPDM =
LOW) period using the “dummy clamp” loop shown in Figure
20. When closed around the CDS, this loop establishes the
desired dc bias point on the coupling capacitor.
CLPDM
TO ADC
Figure 20.
Input Blanking
In some applications, the AD9802’s input may be exposed to
large signals from the CCD. These signals can be very large,
relative to the AD9802’s input range, and could thus saturate
on-chip circuit blocks. Recovery time from such saturation
conditions could be substantial.
To avoid problems associated with processing these transients,
the AD9802 includes an input blanking function. When active
(PBLK = LOW) this function stops the CDS operation and
allows the user to disconnect the CDS inputs from the CCD
buffer.
If the input voltage exceeds the supply rail by more than 0.3V,
then protection diodes will be turned on, increasing current flow
into the AD9802 (see Equivalent Input Circuits). Such voltage
levels should be externally clamped to prevent device damage or
reliability degradation.
10-Bit Analog-to-Digital Converter (ADC)
The ADC employs a multibit pipelined architecture that is
well suited for high throughput rates while being both area and
power efficient. The multistep pipeline presents a low input
capacitance resulting in lower on-chip drive requirements. A
fully differential implementation was used to overcome head-
room constraints of the single +3V power supply.
Direct ADC Input
The analog processing circuitry may be bypassed in the
AD9802. When ADCMODE (Pin 41) is taken high, the
ADCIN pin provides a direct input to the SHA. This feature
allows digitization of signals that do not require CDS and
gain adjustment. The PGA output is disconnected from the
SHA when ADCMODE is taken high.
Differential Reference
The AD9802 includes a 0.5V reference based on a differential,
continuous-time bandgap cell. Use of an external bypass capaci-
tor reduces the reference drive requirements, thus lowering the
power dissipation. The differential architecture was chosen for
its ability to reject supply and substrate noise. Recommended
decoupling shown in Figure 21.
Figure 21.
Internal Timing
The AD9802’s on-chip timing circuitry generates all clocks
necessary for operation of the CDS and ADC blocks. The user
needs only to synchronize the SHP and SHD clocks with the
CCD waveform, as all other timing is handled internally. The
ADCCLK signal is used to strobe the output data, and can be
adjusted to accommodate desired timing.
AD9802
APPLICATIONS INFORMATION
Generating Clock Signals
For best performance, the AD9802 should be driven by 3 V
logic levels. As shown in the Equivalent Input Circuits, the use
of 5 V logic for ADCCLK will turn on the protection diode to
DVDD, increasing the current flow into this pin. As a result,
noise and power dissipation will increase. The CDS clock in-
puts, SHP and SHD, have a additional protection and can with-
stand direct 5 V levels.
External clamping diodes or resistor dividers can be used to
translate 5 V levels to 3 V levels, but the lowest power dissi-
pation is achieved with a logic transceiver chip. National
Semiconductor’s 74LVX4245 provides a 5 V to 3 V level shift
for up to eight clock signals, has a three-state option, and
features low power consumption. Philips Semiconductor and
Quality also manufacture similar devices.
Driving the Direct ADC Input
The AD9802 can be used in a “direct ADC input” mode, in
which the input signal bypasses the input clamp, CDS and
PGA, and is sent directly to the sample and hold amplifier (SHA)
of the ADC. There are several methods that may be used to
drive the direct ADC input.
To enable the direct input mode of operation, ADCMODE (Pin
41) is taken to logic high. This will internally disconnect the
PGA output from the SHA input, and connect ADCIN (Pin 36)
to the SHA input.
The SHA has a differential input, consisting of ADCIN (Pin 36)
as the positive input, and SHABYP (Pin 38) as the negative
input. Both pins must be properly dc biased.
Figures 22 through 25 show four circuits for driving the direct
ADC input. Decoupling capacitors are not shown for CML,
VRT, VRB and SHABYP pins.
1V p-p
CML
Figure 22.DC-Coupled Input
Figure 22 is a single-ended, dc-coupled circuit. SHABYP is
connected to CML (1.5 V) to establish a midpoint bias. The
input signal of 1 V p-p should be centered around CML.
Figure 23 shows an ac-coupled configuration, where both inputs
are biased to CML. The input capacitor CIN and bias resistors
should be sized to set the appropriate high pass cutoff frequency
for the application. To minimize the differential offset voltage
due to the input bias currents, both resistors should be equal.
1V p-p
Figure 23.AC-Coupled Input
Figure 24 shows an alternative ac-coupled configuration. By
connecting SHABYP to CML, the dc bias at Pin 36 (ADCIN)
will internally track to the same voltage, automatically setting
the input bias level. With a given input capacitor value, CIN, the
time constant in this configuration will be dependent on the
sampling frequency FS. Specifically:
τ = (CIN/FS) × 2E +12
1V p-p
Figure 24.“Auto Bias” AC-Coupled Input
Figure 25 shows a true differential drive circuit. Each input
would be 500 mV p-p, to achieve the 1 V full-scale input to the
ADC. The common-mode input range for this configuration
extends from about 500 mV to 2.5 V. This circuit could also be
implemented with ac coupling, similar to Figure 23.
500mV p-p
+3V
500mV p-p
Figure 25.Differential Input
Figure 26 shows a video clamp circuit which may be used with
the direct ADC mode of the AD9802 (supplies and decoupling
not shown). The circuit will clamp the reference black level of
an incoming video signal to 1.25V dc. With SHABYP con-
nected to 1.75V (VRT), the ADCIN range spans from 1.25V
to 2.25V. To accomplish this, the CLAMP pulse should be
asserted during the horizontal sync interval, when the video is at
its reference black level. A 5 V logic high applied to the gate of
the SD210 will turn on the device, and the input capacitor CIN
will charge up to provide 1.25V at the ADCIN pin of the

Partno	Mfg	Dc	Qty	Available	Descript
AD9802JST	AD	N/a	10000	avai	CCD Signal Processor For Electronic Cameras
AD9802JST	ADI	N/a	13	avai	CCD Signal Processor For Electronic Cameras