AD9779BSVZRL ,Dual 16-Bit, 1.0 GSPS D/A ConverterAPPLICATIONS high quality synthesis of wideband signals from baseband to high • Wireless Infrastruc ..
AD977A ,16-Bit, 200 kSPS, Serial I/O A/D ConverterSPECIFICATIONS (–40C to +85C, F = 100 kHz, V = V = 5 V, unless otherwise noted)S DIG ANA ..
AD977AAN ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D ConverterSPECIFICATIONS (–408C to +858C, F = 200 kHz, V = V = +5 V, unless otherwise noted)S DIG ANA ..
AD977AAR ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converterspecifications of offset, gain– 3.3 V, and unipolar ranges of 0 V to 10 V, 0 V to 5 V andand linear ..
AD977AARS ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D ConverterFEATURES FUNCTIONAL BLOCK DIAGRAMFast 16-Bit ADC100 kSPS Throughput Rate—AD977 VREFANA AGND1200 kSP ..
AD977ABN ,16-Bit, 100 kSPS/200 kSPS BiCMOS A/D ConverterSPECIFICATIONS (–408C to +858C, F = 100 kHz, V = V = +5 V, unless otherwise noted)S DIG ANA ..
ADS8505IDB ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Parallel Interface 2.5V Internal Reference 28-SSOP -40 to 85SLAS180B–SEPTEMBER 2005–REVISED JUNE 2007
ADS8505IDBG4 , 16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
ADS8505IDW ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Parallel Interface 2.5V Internal Reference 28-SOIC -40 to 85SLAS180B–SEPTEMBER 2005–REVISED JUNE 2007These devices have limited built-in ESD protection. The le ..
ADS8505IDW ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Parallel Interface 2.5V Internal Reference 28-SOIC -40 to 85ELECTRICAL CHARACTERISTICST = –40°C to 85°C, f = 250 kHz, V = V = 5 V, using internal reference (un ..
ADS8505IDWG4 ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Parallel Interface 2.5V Internal Reference 28-SOIC -40 to 85MAXIMUM RATINGS(2)over operating free-air temperature range (unless otherwise noted)UNITV ±25VINAna ..
ADS8506IBDW ,12-Bit 40KSPS Analog-to-Digital Converter w/Serial Interface and Reference Parallel 28-SOIC -40 to 85SLAS484B–SEPTEMBER 2007–REVISED DECEMBER 2007These devices have limited built-in ESD protection. Th ..
AD9779BSVZRL
Dual 16-Bit, 1.0 GSPS D/A Converter
Rev. PrD
Dual 16-Bit, 1.0 GSPS
D/A Converter
FEATURES 1.8/3.3 V Single Supply Operation Low power: 950mW (IOUTFS = 20 mA; fDAC = 1 GSPS, 4×
Interpolation DNL = ± 1.5 LSB, INL = ± 5.0 LSB SFDR =82 dBc to fOUT = 100 MHz ACLR = 87 dBc @ 80 MHz IF CMOS data interface with Autotracking Input Timing Analog Output: Adjustable 10-30mA (RL=25 Ω to 50 Ω) 100-lead Exposed Paddle TQFP Package Multiple Chip Synchronization Interface 84dB Digital Interpolation Filter Stopband Attenuation Digital Inverse Sinc Filter
APPLICATIONS Wireless Infrastructure Direct Conversion Transmit Diversity Wideband Communications Systems: Point-to-Point Wireless, LMDS
PRODUCT DESCRIPTION The AD9779 is a dual 16-bit high performance, high frequency
DAC that provides a sample rate of 1 GSPS, permitting multi
carrier generation up to its Nyquist frequency. It includes features
optimized for direct conversion transmit applications, including
complex digital modulation and gain and offset compensation. The
DAC outputs are optimized to interface seamlessly with analog
quadrature modulators such as the AD8349. A serial peripheral
interface (SPI) provides for programming many internal
parameters and also enables read-back of status registers. The
output current can be programmed over a range of 10mA to 30mA.
The AD9779 is manufactured on an advanced 0.18µm CMOS
process and operates from 1.8V and 3.3V supplies for a total power
consumption of 950mW. It is supplied in a 100-lead QFP package.
PRODUCT HIGHLIGHTS Ultra-low noise and Intermodulation Distortion (IMD) enable
high quality synthesis of wideband signals from baseband to high
intermediate frequencies.
Single-ended CMOS interface supports a maximum input rate of
300 MSPS with 1x interpolation.
Manufactured on a CMOS process, the AD9779 uses a proprietary
switching technique that enhances dynamic performance.
The current outputs of the AD9779 can be easily configured for
various single-ended or differential circuit topologies.
FUNCTIONAL BLOCK DIAGRAM P2D[15:0]
IOUT2_P
IOUT2_N
CLK+
CLK-
DATACLK_OUT
SDI
CSB
IOUT1_P
IOUT1_N
VREF
RSET
AUX1_P
AUX1_N
AUX2_P
AUX2_N
P1D[15:0]
SYNC_I
SYNC_O
Figure 1 Functional Block Diagram
TABLE OF CONTENTS Specifications............................................................................................3
DC SPECIFICATIONS......................................................................3
DIGITAL SPECIFICATIONS............................................................4
AC SPECIFICATIONS.......................................................................4
Pin Function Descriptions.....................................................................5
Pin Configuration....................................................................................6
Interpolation Filter Coefficients............................................................7
INTERPOLATION Filter RESPONSE CURVES................................8
CHARACTERIZATION DATA............................................................9
General Description..............................................................................12
Serial Peripheral Interface................................................................12
General Operation of the Serial Interface......................................12
Instruction Byte.................................................................................12
Serial Interface Port Pin Descriptions............................................12
MSB/LSB Transfers...........................................................................13
Notes on Serial Port Operation.......................................................13
SPI Register Map...............................................................................14
Internal Reference/Full Scale Current Generation.......................22
Auxiliary DACs..................................................................................22
Power Down and Sleep Modes........................................................22
Internal PLL Clock Multiplier / Clock Distribution.....................23
Timing Information..........................................................................23
Interpolation Filter Architecture.....................................................25
EvaLuation Board Schematics..............................................................27
REVISION HISTORY Revision PrA: Initial Version
Revision PrB: Updated Page 1 Features, added eval board schematics, SPI register map, filter coefficients and filter response curves
Revision PrC: Added characterization data, description of modulation modes, internal clock distribution architecture, timing information
Revision PrD: Added more ac characterization data, power dissipation
SPECIFICATIONS1
DC SPECIFICATIONS
(VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED) Table 1: DC Specifications
DIGITAL SPECIFICATIONS
(VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED) Table 2: Digital Specifications
AC SPECIFICATIONS
(VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED) Table 3: AC Specifications
PIN FUNCTION DESCRIPTIONS
