AD9762AR Fast Delivery |IC PHOENIX CO.,LIMITED

AD9762AR ,12-Bit, 125 MSPS TxDAC D/A ConverterSPECIFICATIONSMIN MAX OUTFS Parameter Min Typ Max UnitsRESOLUTION 12 Bits1DC ACCURACYIntegral Linea ..
AD9763AST ,10-Bit, 125 MSPS Dual TxDAC+ D/A Converterapplications. The digital interface consists oftwo double-buffered latches as well as control logic ..
AD9763AST ,10-Bit, 125 MSPS Dual TxDAC+ D/A ConverterSPECIFICATIONSMIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 10 Bits1DC ACCURACYIntegral Linear ..
AD9764AR ,14-Bit, 125 MSPS TxDAC D/A ConverterSPECIFICATIONSParameter Min Typ Max UnitsDYNAMIC PERFORMANCEMaximum Output Update Rate (f ) 125 MSP ..
AD9764ARU ,14-Bit, 125 MSPS TxDAC D/A ConverterFEATURESMember of Pin-Compatible TxDAC Product Family+5V125 MSPS Update Rate0.1mF14-Bit ResolutionE ..
AD9765AST ,12-Bit, 125 MSPS Dual TxDAC+ D/A ConverterSPECIFICATIONSMIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 12 Bits1DC ACCURACYIntegral Linear ..
ADS8345EB ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital ConverterMAXIMUM RATINGSELECTROSTATIC+V to GND –0.3V to +6VCC Analog Inputs to GND ...... –0.3V to (+V ) + ..
ADS8345EB ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital ConverterELECTRICAL CHARACTERISTICS: +2.7VAt T = –40°C to +85°C, +V = +2.7V, V = +1.25V, f = 100kHz, and f ..
ADS8345N ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital Converter®ADS8345®ADS8345ADS8345SBAS177C – FEBRUARY 2001 – REVISED APRIL 200316-Bit, 8-Channel Serial Output ..
ADS8345NB ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital ConverterFEATURES* BIPOLAR INPUT RANGEThe ADS8345 is an 8-channel, 16-bit, samplingAnalog-to-Digital (A/D) c ..
ADS8345NBG4 ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital Converter 20-SSOP -40 to 85.PIN DESCRIPTIONSPIN CONFIGURATIONPIN NAME DESCRIPTIONTop View SSOP1 CH0 Analog Input Channel 02 CH ..
ADS8354IRTER ,SAR ADC, Dual, 700 kSPS, 16 Bit, Simultaneous Sampling 16-WQFN -40 to 125Features 2 Applications1• 16-, 14-, and 12-Bit, Pin-Compatible Family • Motor Control:Position Meas ..

AD9762AR
12-Bit, 125 MSPS TxDAC D/A Converter
REV.B
12-Bit, 125 MSPS
TxDAC® D/A Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
12-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output:70 dBc
Differential Current Outputs:2 mA to 20 mA
Power Dissipation:175 mW @ 5V to 45mW @ 3V
Power-Down Mode:25 mW @ 5V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Package:28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Communication Transmit Channel:
Basestations (Single/Multichannel Applications)
ADSL/HFC Modems
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
The AD9762 is the 12-bit resolution member of the TxDAC
series of high performance, low power CMOS digital-to-analog
converters (DACs). The TxDAC family which consists of pin
compatible 8-, 10-, 12-, and 14-bit DACs is specifically opti-
mized for the transmit signal path of communication systems.
All of the devices share the same interface options, small outline
package and pinout, thus providing an upward or downward
component selection path based on performance, resolution and
cost. The AD9762 offers exceptional ac and dc performance
while supporting update rates up to 125 MSPS.
The AD9762’s flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW without a significant degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 25 mW.
The AD9762 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input
latches and a 1.2 V temperature compensated bandgap refer-
ence have been integrated to provide a complete monolithic
DAC solution. Flexible supply options support +3 V and +5 V
CMOS logic families.
The AD9762 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.
TxDAC is a registered trademark of Analog Devices, Inc.
*Patent pending.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9762 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier which provides a wide
(>10:1) adjustment span allows the AD9762 full-scale current
to be adjusted over a 2mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9762 may oper-
ate at reduced power levels or be adjusted over a 20dB range to
provide additional gain ranging capabilities.
The AD9762 is available in 28-lead SOIC and TSSOP pack-
ages. It is specified for operation over the industrial tempera-
ture range.
PRODUCT HIGHLIGHTSThe AD9762 is a member of the TxDAC product family which
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.Manufactured on a CMOS process, the AD9762 uses a pro-
prietary switching technique that enhances dynamic perfor-
mance beyond what was previously attainable by higher
power/cost bipolar or BiCMOS devices.On-chip, edge-triggered input CMOS latches interface readily
to +3 V and +5 V CMOS logic families. The AD9762 can
support update rates up to 125 MSPS.A flexible single-supply operating range of 2.7V to 5.5 V and
a wide full-scale current adjustment span of 2mA to 20 mA
allow the AD9762 to operate at reduced power levels.The current output(s) of the AD9762 can be easily config-
DC SPECIFICATIONS
REFERENCE INPUT
TEMPERATURE COEFFICIENTS
NOTESMeasured at IOUTA, driving a virtual ground.Nominal full-scale current, IOUTFS, is 32 × the IREF current.Use an external buffer amplifier to drive any external load.Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41.For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz.Measured as unbuffered voltage output into 50Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.
Specifications subject to change without notice.
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
AD9762–SPECIFICATIONS
DYNAMIC SPECIFICATIONS
AC LINEARITY
NOTESMeasured single ended into 50Ω load.
Specifications subject to change without notice.
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output,� Doubly Terminated, unless otherwise noted)
AD9762
AD9762
DIGITAL SPECIFICATIONS
Specifications subject to change without notice.
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
ORDERING GUIDE
*R = SOIC, RU = TSSOP.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 mil SOIC
θJA = 71.4°C/W
θJC = 23°C/W
28-Lead TSSOP
θJA = 97.9°C/W
θJC = 14.0°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted)
PIN CONFIGURATION
PIN DESCRIPTIONS
AD9762
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured output signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range for an output containing mul-
tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.
Figure 2.Basic AC Characterization Test Set-Up
Typical AC Characterization Curves @ +5 V Supplies
(AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, 50� Doubly Terminated Load, Differential Output, TA = +25�C, SFDR up to Nyquist, unless otherwise noted)
Figure 3.SFDR vs. fOUT @ 0 dBFS
Figure 6.SFDR vs. fOUT @ 50 MSPS
Figure 9.Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/11
Figure 4.SFDR vs. fOUT @ 5MSPS
Figure 7.SFDR vs. fOUT @100 MSPS
Figure 10.Single-Tone SFDR vs.
AOUT @ fOUT = fCLOCK/5
Figure 5.SFDR vs. fOUT @ 25 MSPS
Figure 8.SFDR vs. fOUT @ 125 MSPS
Figure 11.Dual-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/7
AD9762
Figure 12. THD vs. fCLOCK @
fOUT = 2MHz
Figure 15.Typical INL
Figure 18.Single-Tone SFDR
Figure 13.SFDR vs. fOUT and IOUTFS
@ 100 MSPS, 0 dBFS
ERROR
LSB
CODE
Figure 16.Typical DNL
Figure 19.Dual-Tone SFDR
Figure 14.Differential vs. Single-
Ended SFDR vs. fOUT @ 100 MSPS
Figure 17.SFDR vs. Temperature
@ 100 MSPS, 0 dBFS
Figure 20.Four-Tone SFDR
Figure 21.SFDR vs. fOUT @ 0 dBFS
Figure 24.SFDR vs. fOUT @ 50 MSPS
Figure 27.Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/11
Typical AC Characterization Curves @ +3 V Supplies
(AVDD = +3 V, DVDD = +3 V, IOUTFS = 20 mA, 50Ω Doubly Terminated Load, Differential Output, TA = +25�C, SFDR up to Nyquist, unless otherwise noted)
Figure 22.SFDR vs. fOUT @ 5 MSPS
Figure 25.SFDR vs. fOUT @ 100 MSPS
Figure 28.Single-Tone SFDR vs.
AOUT @ fOUT = fCLOCK/5
Figure 23.SFDR vs. fOUT @ 25 MSPS
Figure 26.SFDR vs. fOUT @ 125 MSPS
Figure 29.Dual-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/7
AD9762
Figure 30.THD vs. fCLOCK @ fOUT =MHz
Figure 33.Typical INL
Figure 36.Single-Tone SFDR
Figure 31.SFDR vs. fOUT and IOUTFS
@ 100 MSPS, 0 dBFS
Figure 34.Typical DNL
Figure 37.Dual-Tone SFDR
Figure 32.Differential vs. Single
Ended SFDR vs. fOUT @ 100 MSPS
Figure 35.SFDR vs. Temperature
@ 100 MSPS, 0 dBFS
Figure 38.Four-Tone SFDR
FUNCTIONAL DESCRIPTION
Figure 39 shows a simplified block diagram of the AD9762.
The AD9762 consists of a large PMOS current source array
that is capable of providing up to 20mA of total current. The
array is divided into 31 equal currents that make up the 5
most significant bits (MSBs). The next 4 bits or middle bits
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSBs are binary weighted
fractions of the middle-bits current sources. Implementing
the middle and lower bits with current sources, instead of an
R-2R ladder, enhances its dynamic performance for multitone
or low amplitude signals and helps maintain the DAC’s high
output impedance (i.e., >100kΩ).
All of these current sources are switched to one or the other
of the two output nodes (i.e., IOUTA or IOUTB) via PMOS differen-
tial current switches. The switches are based on a new archi-
tecture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9762 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 volt to 5.5 volt range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V bandgap
voltage reference and a reference control amplifier.
The full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, RSET. The external resistor, in combination
with both the reference control amplifier and voltage refer-
ence VREFIO, sets the reference current IREF, which is mirrored
over to the segmented current sources with the proper scaling
factor. The full-scale current, IOUTFS, is thirty-two times the value
of IREF.
DAC TRANSFER FUNCTION
The AD9762 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 4095) while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of
both the input code and IOUTFS and can be expressed as:
IOUTA = (DAC CODE/4096) × IOUTFS(1)
IOUTB = (4095 – DAC CODE)/4096 × IOUTFS(2)
where DAC CODE = 0 to 4095 (i.e., Decimal Representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage
VREFIO and external resistor RSET. It can be expressed as:
IOUTFS = 32 × IREF(3)
where IREF = VREFIO/RSET(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, which are tied to analog common, ACOM. Note,
RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminatedΩ or 75Ω cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply :
VOUTA = IOUTA × RLOAD(5)
VOUTB = IOUTB × RLOAD(6)
Note the full-scale value of VOUTA and VOUTB should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
The differential voltage, VDIFF, appearing across IOUTA and
IOUTB is:
VDIFF = (IOUTA – IOUTB) × RLOAD(7)
Substituting the values of IOUTA, IOUTB, and IREF; VDIFF can be
expressed as:
VDIFF = {(2 DAC CODE – 4095)/4096} ×
(32 RLOAD/RSET) × VREFIO(8)
These last two equations highlight some of the advantages of
operating the AD9762 differentially. First, the differential
operation will help cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion and dc offsets.
Second, the differential code dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (i.e., VOUTA or VOUTB), thus providing twice the signal
power to the load.
Note, the gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the AD9762
can be enhanced by selecting temperature tracking resistors for
RLOAD and RSET due to their ratiometric relationship as shown
in Equation 8.
AD9762
REFERENCE OPERATION
The AD9762 contains an internal 1.20 V bandgap reference
that can be easily disabled and overridden by an external refer-
ence. REFIO serves as either an input or output depending on
whether the internal or an external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 40, the internal
reference is activated and REFIO provides a 1.20V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1µF or greater from REFIO
to REFLO. Also, REFIO should be buffered with an external
amplifier having an input bias current less than 100nA if any
additional loading is required.
Figure 40.Internal Reference Configuration
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 41. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1µF compensation capacitor is not required
since the internal reference is disabled, and the high input
impedance (i.e., 1 MΩ) of REFIO minimizes any loading of the
external reference.
Figure 41.External Reference Configuration
REFERENCE CONTROL AMPLIFIER
The AD9762 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a V-I converter as shown
in Figure 41, such that its current output, IREF, is determined by
the ratio of the VREFIO and an external resistor, RSET, as stated
in Equation 4. IREF is copied over to the segmented current
sources with the proper scaling factor to set IOUTFS as stated in
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2mA to 20 mA range by setting IREF between
62.5µA and 625µA. The wide adjustment span of IOUTFS
provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9762, which is
proportional to IOUTFS (refer to the Power Dissipation section).
The second benefit relates to the 20dB adjustment, which is
useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 1.4 MHz and can be reduced by connecting an
external capacitor between COMP1 and AVDD. The output of
the control amplifier, COMP1, is internally compensated via a
50 pF capacitor that limits the control amplifier small-signal
bandwidth and reduces its output impedance. Any additional
external capacitance further limits the bandwidth and acts as a
filter to reduce the noise contribution from the reference ampli-
fier. Figure 42 shows the relationship between the external
capacitor and the small signal –3dB bandwidth of the
Figure 42.External COMP1 Capacitor vs. –3dB Bandwidth
reference amplifier. Since the –3dB bandwidth corresponds
to the dominant pole, and hence the time constant, the settling
time of the control amplifier to a stepped reference input
response can be approximated.
The optimum distortion performance for any reconstructed
waveform is obtained with a 0.1µF external capacitor installed.
Thus, if IREF is fixed for an application, a 0.1µF ceramic chip
capacitor is recommended. Also, since the control amplifier is
optimized for low power operation, multiplying applications
requiring large signal swings should consider using an external
control amplifier to enhance the application’s overall large signal
multiplying bandwidth and/or distortion performance.
There are two methods in which IREF can be varied for a fixed
RSET. The first method is suitable for a single-supply system in
which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, thus allowing IREF to be varied for a fixed RSET. Since the
input impedance of REFIO is approximately 1 MΩ, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown

Partno	Mfg	Dc	Qty	Available	Descript
AD9762AR	ADI	N/a	9160	avai	12-Bit, 125 MSPS TxDAC D/A Converter