AD9223AR-REEL ,12-Bit, 3.0 MSPS A/D ConverterGENERAL DESCRIPTION and beyond the Nyquist rate. Also, the AD9221/AD9223/AD9220The AD9221, AD9223, ..
AD9223ARS ,Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D ConvertersSPECIFICATIONS Ended Input T to T unless otherwise noted)MIN MAXParameters AD9221 AD9223 AD9220 Uni ..
AD9224ARS ,Complete 12-Bit 40 MSPS Monolithic A/D ConverterFEATURESMonolithic 12-Bit, 40 MSPS A/D ConverterAVDD DRVDDCLKLow Power Dissipation: 415 mWSHASingle ..
AD9225AR ,Complete 12-Bit, 25 MSPS Monolithic A/D ConverterFEATURESMonolithic 12-Bit, 25 MSPS A/D ConverterCLK AVDD DRVDDLow Power Dissipation: 280 mWSingle + ..
AD9225ARS ,Complete 12-Bit, 25 MSPS Monolithic A/D ConverterSPECIFICATIONS (AVDD = +5 V, DRVDD = +5 V, f = 25 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, T to T unles ..
AD9226 ,12-Bit, 65 MSPS Analog-to-Digital ConverterFEATURES FUNCTIONAL BLOCK DIAGRAMSignal-to-Noise Ratio: 69 dB @ f = 31 MHzINDRVDDCLK AVDDSpurious-F ..
ADS7807PB ,Brown Corporation - Low-Power, 16-Bit, Sampling CMOS ANALOG-to-DIGITAL CONVERTER
ADS7807U ,Low-Power 16-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTERFEATURESDESCRIPTION* 35mW max POWER DISSIPATIONThe ADS7807 is a low-power, 16-bit, sampling Analog- ..
ADS7807UB ,Low-Power 16-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTERPIN DESCRIPTIONSDIGITALPIN # NAME I/O DESCRIPTION1R1 Analog Input. See Figure 7.IN2 AGND1 Analog Se ..
ADS7808P ,12-Bit 10ms Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTERADS7808SBAS018A – JANUARY 1992 – REVISED SEPTEMBER 200312-Bit 10µ s Serial CMOS SamplingANALOG-to-D ..
ADS7808P ,12-Bit 10ms Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTERMAXIMUM RATINGSELECTROSTATICAnalog Inputs: R1 .. ±25VINR2 .. ±25VDISCHARGE SENSITIVITYINR3 .. ±25VI ..
ADS7808U ,12-Bit 10ms Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTERELECTRICAL CHARACTERISTICSAt T = –40°C to +85°C, f = 100kHz, V = V = +5V, using internal reference ..
AD9223AR-REEL
Complete 12-Bit, 10.0 MSPS Monolithic A/D Converter
REV.E
Complete 12-Bit 1.5/3.0/10.0 MSPS
Monolithic A/D Converters
FEATURES
Monolithic 12-Bit A/D Converter Product Family
Family Members Are: AD9221, AD9223, and AD9220
Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS, and
10.0 MSPS
Low Power Dissipation: 59 mW, 100 mW, and 250 mW
Single 5 V Supply
Integral Nonlinearity Error: 0.5 LSB
Differential Nonlinearity Error: 0.3 LSB
Input Referred Noise: 0.09 LSB
Complete On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 70 dB
Spurious-Free Dynamic Range: 86 dB
Out-of-Range Indicator
Straight Binary Output Data
28-Lead SOIC and 28-Lead SSOP
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD9221, AD9223, and AD9220 are a generation of high
performance, single supply 12-bit analog-to-digital converters.
Each device exhibits true 12-bit linearity and temperature drift
performance1 as well as 11.5-bit or better ac performance.2 The
AD9221/AD9223/AD9220 share the same interface options,
package, and pinout. Thus, the product family provides an upward
or downward component selection path based on performance,
sample rate and power. The devices differ with respect to their
specified sampling rate, and power consumption, which is reflected
in their dynamic performance over frequency.
The AD9221/AD9223/AD9220 combine a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid and monolithic implementations at
a fraction of the power consumption and cost. Each device is a
complete, monolithic ADC with an on-chip, high performance,
low noise sample-and-hold amplifier and programmable voltage
reference. An external reference can also be chosen to suit the
dc accuracy and temperature drift requirements of the application.
The devices use a multistage differential pipelined architecture
with digital output error correction logic to provide 12-bit accu-
racy at the specified data rates and to guarantee no missing
codes over the full operating temperature range.
The input of the AD9221/AD9223/AD9220 is highly flexible,
allowing for easy interfacing to imaging, communications, medi-
cal, and data-acquisition systems. A truly differential input
structure allows for both single-ended and differential input
interfaces of varying input spans. The sample-and-hold
amplifier (SHA) is equally suited for both multiplexed sys-
tems that switch full-scale voltage levels in successive channels
as well as sampling single-channel inputs at frequencies up to
and beyond the Nyquist rate. Also, the AD9221/AD9223/AD9220
is well suited for communication systems employing Direct-
IF down conversion since the SHA in the differential input
mode can achieve excellent dynamic performance far beyond its
specified Nyquist frequency.2
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an over-
flow condition that can be used with the most significant bit to
determine low or high overflow.
PRODUCT HIGHLIGHTSThe AD9221/AD9223/AD9220 family offers a complete single-
chip sampling 12-bit, analog-to-digital conversion function in
pin compatible 28-lead SOIC and SSOP packages.
Flexible Sampling Rates—The AD9221, AD9223, and AD9220
offer sampling rates of 1.5 MSPS, 3.0 MSPS, and 10.0 MSPS,
respectively.
Low Power and Single Supply—The AD9221, AD9223, and
AD9220 consume only 59 mW, 100 mW, and 250 mW, respec-
tively, on a single 5 V power supply.
Excellent DC Performance Over Temperature—The AD9221/
AD9223/AD9220 provide 12-bit linearity and temperature drift
performance.1
Excellent AC Performance and Low Noise—The AD9221/
AD9223/AD9220 provide better than 11.3 ENOB performance
and have an input referred noise of 0.09 LSB rms.2
Flexible Analog Input Range—The versatile on-board sample-
and-hold (SHA) can be configured for either single-ended or
differential inputs of varying input spans.
NOTESExcluding internal voltage reference.Depends on the analog input configuration.
AD9221/AD9223/AD9220–SPECIFICATIONS
(AVDD = 5 V, DVDD = 5 V, fSAMPLE = Max Conversion Rate, VREF = 2.5 V, VINB = 2.5 V, TMIN to TMAX, unless
otherwise noted.)ACCURACY
TEMPERATURE DRIFT
POWER SUPPLY REJECTION
ANALOG INPUT
POWER CONSUMPTION
NOTESVREF = 1 V.Including internal reference.
DC SPECIFICATIONS
AD9221/AD9223/AD9220
AC SPECIFICATIONS
(AVDD = 5 V, DVDD= 5 V, fSAMPLE = Max Conversion Rate, VREF = 1.0 V, VINB = 2.5 V, DC Coupled/Single-
Ended Input TMIN to TMAX, unless otherwise noted.)Specifications subject to change without notice.
DIGITAL SPECIFICATIONS(AVDD = 5 V, DVDD = 5 V, TMIN to TMAX, unless otherwise noted.)LOGIC OUTPUTS
AD9221/AD9223/AD9220
SWITCHING SPECIFICATIONS(TMIN to TMAX with AVDD = 5 V, DVDD = 5 V, CL = 20 pF)*The clock period may be extended to 1 ms without degradation in specified performance @ 25°C.
Specifications subject to change without notice.
Figure 1.Timing Diagram
ABSOLUTE MAXIMUM RATINGS*Storage Temperature
Lead Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
THERMAL CHARACTERISTICSThermal Resistance
28-Lead SOIC
�JA = 71.4°C/W
�JC = 23°C/W
28-Lead SSOP
�JA = 63.3°C/W
�JC = 23°C/W
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9221/AD9223/AD9220 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS2BIT 12
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity (INL)INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as negative full scale occurs 1/2 LSB before the
first code transition. Positive full scale is defined as a level 1 1/2
LSB beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes, respectively, must be present over all operating ranges.
Zero ErrorThe major carry transition should occur for an analog value 1/2
LSB below VINA = VINB. Zero error is defined as the devia-
tion of the actual transition from that point.
Gain ErrorThe first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last transition should occur at an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.
Temperature DriftThe temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
TMIN or TMAX.
Power Supply RejectionThe specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
Aperture JitterAperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
Aperture DelayAperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Signal-to-Noise and Distortion (S/N+D, SINAD) RatioS/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels.
Effective Number of Bits (ENOB)For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
Total Harmonic Distortion (THD)THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
Signal-to-Noise Ratio (SNR)SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Spurious Free Dynamic Range (SFDR)SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
AD9221/AD9223/AD9220
(AVDD = 5 V, DVDD = 5 V, fSAMPLE = 1.5 MSPS, TA = 25�C)AD9221–Typical Performance Characteristics
CODE
DNL – LSBsTPC 1.Typical DNL
TPC 4.SINAD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
TPC 7.THD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
CODE
INL – LSBsTPC 2.Typical INL
TPC 5.THD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
TPC 8.THD vs. Sample Rate
(AIN = –0.5 dB, fIN = 500 kHz,
VCM = 2.5 V)
TPC 3.“Grounded-Input”
Histogram (Input Span = 2 V p-p)
TPC 6.SINAD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
TPC 9.SNR/SFDR vs. AIN (Input
Amplitude) (fIN = 500 kHz, Input
Span = 2 V p-p, VCM = 2.5 V)
CODE
DNL – LSBsTPC 10.Typical DNL
TPC 13.SINAD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
TPC 16.THD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
CODE
INL – LSBsTPC 11.Typical INL
FREQUENCY – MHz
THD – dB
–100TPC 14.THD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
SAMPLE RATE – MSPS
THD – dB
0.612356TPC 17.THD vs. Sample Rate
(AIN = –0.5 dB, fIN = 500 kHz,
VCM = 2.5 V)
TPC 12.“Grounded-Input”
Histogram (Input Span = 2 V p-p)
TPC 15.SINAD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
TPC 18.SNR/SFDR vs. AIN (Input
Amplitude) (fIN = 1.5 MHz, Input
Span = 2 V p-p, VCM = 2.5 V)
AD9223–Typical Performance Characteristics(AVDD = 5 V, DVDD = 5 V, fSAMPLE = 3.0 MSPS, TA = 25�C)
AD9221/AD9223/AD9220
AD9220–Typical Performance Characteristics(AVDD = 5 V, DVDD = 5 V, fSAMPLE = 10 MSPS, TA = 25�C)
CODE
DNL – LSBsTPC 19.Typical DNL
TPC 22.SINAD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
FREQUENCY – MHz
THD – dB
–80TPC 25.THD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
CODE
INL – LSBsTPC 20.Typical INL
FREQUENCY – MHz
THD – dBTPC 23.THD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
SAMPLE RATE – MSPS
THD – dB
–90TPC 26.THD vs. Clock Frequency
(AIN = –0.5 dB, fIN = 1.0 MHz,
VCM = 2.5 V)
TPC 21.“Grounded-Input”
Histogram (Input Span = 2 V p-p)
FREQUENCY – MHz
SINAD – dB
0.11.010.0TPC 24.SINAD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
AIN – dBFS
SNR/SFDR – dB–50–30–10TPC 27.SNR/SFDR vs. AIN (Input
Amplitude) (fIN = 5.0 MHz, Input
Span = 2 V p-p, VCM = 2.5 V)
INTRODUCTIONThe AD9221/AD9223/AD9220 are members of a high perfor-
mance, complete single-supply 12-bit ADC product family based
on the same CMOS pipelined architecture. The product family
allows the system designer an upward or downward component
selection path based on dynamic performance, sample rate, and
power. The analog input range of the AD9221/AD9223/AD9220
is highly flexible, allowing for both single-ended or differen-
tial inputs of varying amplitudes that can be ac or dc coupled.
Each device shares the same interface options, pinout, and
package offering.
The AD9221/AD9223/AD9220 utilize a four-stage pipeline
architecture with a wideband input sample-and-hold amplifier
(SHA) implemented on a cost-effective CMOS process. Each
stage of the pipeline, excluding the last stage, consists of a low
resolution flash A/D connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
amplifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each of the stages to facilitate digital
correction of flash errors. The last stage simply consists of a
flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output buffer
to drive the output pins. The output drivers can be configured to
interface with 5 V or 3.3 V logic families.
The AD9221/AD9223/AD9220 use both edges of the clock in
their internal timing circuitry (see Figure 1 and Specifications
for exact timing requirements). The A/D samples the analog
input on the rising edge of the clock input. During the clock low
time (between the falling edge and rising edge of the clock), the
input SHA is in the sample mode; during the clock high time, it
is in hold. System disturbances just prior to the rising edge of
the clock and/or excessive clock jitter may cause the input SHA
to acquire the wrong value, and should be minimized.
The internal circuitry of both the input SHA and individual
pipeline stages of each member of the product family are opti-
mized for both power dissipation and performance. An inherent
trade-off exists between the input SHA’s dynamic performance
and its power dissipation. Figures 2 and 3 show this trade-off by
comparing the full-power bandwidth and settling time of the
AD9221/AD9223/AD9220. Both figures reveal that higher full-
power bandwidths and faster settling times are achieved at the
expense of an increase in power dissipation. Similarly, a trade-
off exists between the sampling rate and the power dissipated
in each stage.
As previously stated, the AD9221, AD9223, and AD9220 are
similar in most aspects except for the specified sampling rate,
power consumption, and dynamic performance. The product
family is highly flexible, providing several different input ranges
and interface options. As a result, many of the application issues
also similar. The data sheet is structured such that the designer
can make an informed decision in selecting the proper A/D and
optimizing its performance to fit the specific application.
Figure 2.Full-Power Bandwidth
Figure 3.Settling Time
ANALOG INPUT AND REFERENCE OVERVIEWFigure 4, a simplified model of the AD9221/AD9223/AD9220,
highlights the relationship between the analog inputs, VINA,
VINB, and the reference voltage, VREF. Like the voltage
applied to the top of the resistor ladder in a flash A/D converter,
the value VREF defines the maximum input voltage to the A/D
core. The minimum input voltage to the A/D core is automati-
cally defined to be –VREF.
Figure 4. AD9221/AD9223/AD9220 Equivalent
Functional Input Circuit
AD9221/AD9223/AD9220The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily config-
ure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the
converter. Specifically, the input to the A/D core is the differ-
ence of the voltages applied at the VINA and VINB input
pins. Therefore, the equation,(1)
defines the output of the differential input stage and provides
the input to the A/D core.
The voltage, VCORE, must satisfy the condition,(2)
where VREF is the voltage at the VREF pin.
While an infinite combination of VINA and VINB inputs exist
that satisfy Equation 2, there is an additional limitation placed
on the inputs by the power supply voltages of the AD9221/
AD9223/AD9220. The power supplies bound the valid operat-
ing range for VINA and VINB. The condition,(3)
where AVSS is nominally 0 V and AVDD is nominally 5 V,
defines this requirement. Thus, the range of valid inputs for
VINA and VINB is any combination that satisfies both
Equations 2 and 3.
For additional information showing the relationship between
VINA, VINB, VREF and the digital output of the AD9221/
AD9223/AD9220, see Table IV.
Refer to Table I and Table II at the end of this section for a
summary of both the various analog input and reference con-
figurations.
ANALOG INPUT OPERATIONFigure 5 shows the equivalent analog input of the AD9221/
AD9223/AD9220, which consists of a differential sample-and-
hold amplifier (SHA). The differential input structure of the
SHA is highly flexible, allowing the devices to be easily config-
ured for either a differential or single-ended input. The dc
offset, or common-mode voltage, of the input(s) can be set to
accommodate either single-supply or dual-supply systems. Also,
note that the analog inputs, VINA and VINB, are interchange-
able with the exception that reversing the inputs to the VINA
and VINB pins results in a polarity inversion.
The SHA’s optimum distortion performance for a differential or
single-ended input is achieved under the following two conditions:
(1) the common-mode voltage is centered around midsupply
(i.e., AVDD/2 or approximately 2.5 V) and (2) the input signal
voltage span of the SHA is set at its lowest (i.e., 2 V input span).
This is due to the sampling switches, QS1, being CMOS switches
whose RON resistance is very low but has some signal depen-
dency that causes frequency dependent ac distortion while the
SHA is in the track mode. The RON resistance of a CMOS
switch is typically lowest at its midsupply but increases symmetri-
cally as the input signal approaches either AVDD or AVSS. A
lower input signal voltage span centered at midsupply reduces
the degree of RON modulation.
Figure 6 compares the AD9221/AD9223/AD9220’s THD vs.
frequency performance for a 2 V input span with a common-
mode voltage of 1 V and 2.5 V. Note how each A/D with a
common-mode voltage of 1 V exhibits a similar degradation in
THD performance at higher frequencies (i.e., beyond 750 kHz).
Similarly, note how the THD performance at lower frequencies
becomes less sensitive to the common-mode voltage. As the
input frequency approaches dc, the distortion will be dominated
by static nonlinearities such as INL and DNL. It is important to
note that these dc static nonlinearities are independent of any
RON modulation.
FREQUENCY – MHz
THD – dB
–50Figure 6.AD9221/AD9223/AD9220 THD vs. Frequency for
VCM = 2.5 V and 1.0 V (AIN = –0.5 dB, Input Span = 2.0 V p-p)
Due to the high degree of symmetry within the SHA topology, a
significant improvement in distortion performance for differen-
tial input signals with frequencies up to and beyond Nyquist can
be realized. This inherent symmetry provides excellent cancella-
tion of both common-mode distortion and noise. Also, the
required input signal voltage span is reduced by a half, which
further reduces the degree of RON modulation and its effects
on distortion.
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest
input signal voltage span (i.e., 5 V input span) and matched
input impedance for VINA and VINB. Note that only a slight
degradation in dc linearity performance exists between the 2 V
and 5 V input span as specified in the AD9221/AD9223/
Referring to Figure 5, the differential SHA is implemented using a
switched-capacitor topology. Therefore, its input impedance
and its subsequent effects on the input drive source should be
understood to maximize the converter’s performance. The com-
bination of the pin capacitance, CPIN, parasitic capacitance, CPAR,
and sampling capacitance, CS, is typically less than 16 pF.
When the SHA goes into track mode, the input source must
charge or discharge the voltage stored on CS to the new input
voltage. This action of charging and discharging CS, averaged
over a period of time and for a given sampling frequency, fS,
makes the input impedance appear to have a benign resistive
component. However, if this action is analyzed within a sampling
period (i.e., T = 1/fS), the input impedance is dynamic and there-
fore certain precautions on the input drive source should be
observed.
The resistive component to the input impedance can be com-
puted by calculating the average charge that gets drawn by CH
from the input drive source. It can be shown that if CS is allowed
to fully charge up to the input voltage before switches QS1 are
opened, then the average current into the input is the same as if
there were a resistor of 1/(CS fS) ohms connected between the
inputs. This means that the input impedance is inversely pro-
portional to the converter’s sample rate. Since CS is only 4 pF,
this resistive component is typically much larger than that of the
drive source (i.e., 25 kΩ at fS = 10 MSPS).
If one considers the SHA’s input impedance over a sampling
period, it appears as a dynamic input impedance to the input
drive source. When the SHA goes into the track mode, the input
source should ideally provide the charging current through RON
of switch QS1 in an exponential manner. The requirement of
exponential charging means that the most common input source,
an op amp, must exhibit a source impedance that is both low
and resistive up to and beyond the sampling frequency.
The output impedance of an op amp can be modeled with a
series inductor and resistor. When a capacitive load is switched
onto the output of the op amp, the output will momentarily
drop due to its effective output impedance. As the output recov-
ers, ringing may occur. To remedy the situation, a series resistor
can be inserted between the op amp and the SHA input as shown
in Figure 7. The series resistance helps isolate the op amp from
the switched-capacitor load.
Figure 7.Series Resistor Isolates Switched-Capacitor SHA
Input from Op Amp. Matching Resistors Improve SNR
Performance
The optimum size of this resistor is dependent on several factors,
applications may require a larger resistor value to reduce the noise
bandwidth or possibly limit the fault current in an overvoltage
condition. Other applications may require a larger resistor value
as part of an antialiasing filter. In any case, since the THD
performance is dependent on the series resistance and the above
mentioned factors, optimizing this resistor value for a given
application is encouraged.
A slight improvement in SNR performance and dc offset
performance is achieved by matching the input resistance of VINA
and VINB. The degree of improvement is dependent on the
resistor value and the sampling rate. For series resistor values
greater than 100 Ω, the use of a matching resistor is encouraged.
Figure 8 shows a plot for THD performance versus RSERIES for
the AD9221/AD9223/AD9220 at their respective sampling rate
and Nyquist frequency. The Nyquist frequency typically repre-
sents the worst case scenario for an ADC. In this case, a high
speed, high performance amplifier (AD8047) was used as the
buffer op amp. Although not shown, the AD9221/AD9223/AD9220
exhibits a slight increase in SNR (i.e. 1 dB to 1.5 dB) as the
resistance is increased from 0 kΩ to 2.56 kΩ due to its bandlimiting
effect on wideband noise. Conversely, it exhibits slight decrease
in SNR (i.e., 0.5 dB to 2 dB) if VINA and VINB do not have a
matched input resistance.
Figure 8.THD vs. RSERIES (fIN = fS/2, AIN = –0.5 dB, Input
Span = 2 V p-p, VCM = 2.5 V)
Figure 8 shows that a small RSERIES between 30 Ω and 50 Ω
provides the optimum THD performance for the AD9220.
Lower values of RSERIES are acceptable for the AD9223 and
AD9221 as their lower sampling rates provide a longer transient
recovery period for the AD8047. Note that op amps with lower
bandwidths will typically have a longer transient recovery period
and therefore require a slightly higher value of RSERIES and/or
lower sampling rate to achieve the optimum THD performance.
As the value of RSERIES increases, a corresponding increase in
distortion is noted. This is due to its interaction with the SHA’s
parasitic capacitor, CPAR, which has a signal dependency. Thus,
the resulting R-C time constant is signal dependent and conse-
quently a source of distortion.
The noise or small-signal bandwidth of the AD9221/AD9223/
AD9220 is the same as their full-power bandwidth as shown in
AD9221/AD9223/AD9220shunt capacitor can help limit the wideband noise at the A/D’s
input by forming a low-pass filter. Note, however, that the
combination of this series resistance with the equivalent input
capacitance of the AD9221/AD9223/AD9220 should be evalu-
ated for those time-domain applications that are sensitive to the
input signal’s absolute settling time. In applications where har-
monic distortion is not a primary concern, the series resistance
may be selected in combination with the SHA’s nominal 16 pF of
input capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e., VINA
and/or VINB) and analog ground. Since this additional shunt
capacitance combines with the equivalent input capacitance of
the AD9221/AD9223/AD9220, a lower series resistance can
be selected to establish the filter’s cutoff frequency while not
degrading the distortion performance of the device. The shunt
capacitance also acts like a charge reservoir, sinking or sourcing
the additional charge required by the hold capacitor, CH, further
reducing current transients seen at the op amp’s output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9221/AD9223/AD9220 should be evaluated. To
optimize performance when noise is the primary consideration,
increase the shunt capacitance as much as the transient response
of the input signal will allow. Increasing the capacitance too
much may adversely affect the op amp’s settling time, frequency
response, and distortion performance.
REFERENCE OPERATIONThe AD9221/AD9223/AD9220 contain an on-board band gap
reference that provides a pin-strappable option to generate
either a 1 V or 2.5 V output. With the addition of two external
resistors, the user can generate reference voltages other than 1 V
and 2.5 V. Another alternative is to use an external reference for
designs requiring enhanced accuracy and/or drift performance.
See Table II for a summary of the pin-strapping options for the
AD9221/AD9223/AD9220 reference configurations.
Figure 9 shows a simplified model of the internal voltage reference
of the AD9221/AD9223/AD9220. A pin-strappable reference
amplifier buffers a 1 V fixed reference. The output from the
reference amplifier, A1, appears on the VREF pin. The voltage
on the VREF pin determines the full-scale input span of the
A/D. This input span equals,
Full-Scale Input Span = 2 � VREF
The voltage appearing at the VREF pin as well as the state of
the internal reference amplifier, A1, are determined by the volt-
age appearing at the SENSE pin. The logic circuitry contains
two comparators that monitor the voltage at the SENSE pin.
The comparator with the lowest set point (approximately 0.3 V)
controls the position of the switch within the feedback path
of A1. If the SENSE pin is tied to REFCOM, the switch is
connected to the internal resistor network, thus providing a
VREF of 2.5 V. If the SENSE pin is tied to the VREF pin via a
short or resistor, the switch is connected to the SENSE pin. A
short will provide a VREF of 1.0 V while an external resistor
network will provide an alternative VREF between 1.0 V and
disable the reference amplifier if the SENSE pin is tied to AVDD.
Disabling the reference amplifier allows the VREF pin to be
driven by an external voltage reference.
Figure 9.Equivalent Reference Circuit
The actual reference voltages used by the internal circuitry of
the AD9221/AD9223/AD9220 appear on the CAPT and CAPB
pins. For proper operation when using the internal or an external
reference, it is necessary to add a capacitor network to decouple
these pins. Figure 10 shows the recommended decoupling net-
work. This capacitive network performs the following three
functions: (1) along with the reference amplifier, A2, it provides
a low source impedance over a large frequency range to drive
the A/D internal circuitry, (2) it provides the necessary compen-
sation for A2, and (3) it band-limits the noise contribution from
the reference. The turn-on time of the reference voltage appear-
ing between CAPT and CAPB is approximately 15 ms and
should be evaluated in any power-down mode of operation.
Figure 10.Recommended CAPT/CAPB Decoupling
Network
The A/D’s input span may be varied dynamically by changing
the differential reference voltage appearing across CAPT and
CAPB symmetrically around 2.5 V (i.e., midsupply). To change
the reference at speeds beyond the capabilities of A2, it will be
necessary to drive CAPT and CAPB with two high speed, low
noise amplifiers. In this case, both internal amplifiers (i.e., A1
and A2) must be disabled by connecting SENSE to AVDD and
VREF to REFCOM, and the capacitive decoupling network
removed. The external voltages applied to CAPT and CAPB
must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4, respec-
tively, in which the input span can be varied between 2 V and
5 V. Note that those samples within the pipeline A/D during
any reference transition will be corrupted and should be
Table I.Analog Input Configuration SummarySingle-Ended
*VINA and VINB can be interchanged if signal inversion is required.
AD9221/AD9223/AD9220
DRIVING THE ANALOG INPUTS
IntroductionThe AD9221/AD9223/AD9220 has a highly flexible input
structure, allowing it to interface with single-ended or differen-
tial input interface circuitry. The applications shown in sections
Driving the Analog Inputs and Reference Configurations, along
with the information presented in Input and Reference Over-
view of this data sheet, give examples of both single-ended and
differential operation. Refer to Tables I and II for a list of the
different possible input and reference configurations and their
associated figures in the data sheet.
The optimum mode of operation, analog input range, and asso-
ciated interface circuitry will be determined by the particular
application’s performance requirements as well as power supply
options. For example, a dc coupled single-ended input would be
appropriate for most data acquisition and imaging applications.
Also, many communication applications that require a dc coupled
input for proper demodulation can take advantage of the excel-
lent single-ended distortion performance of the AD9221/AD9223/
AD9220. The input span should be configured such that the
system’s performance objectives and the headroom requirements
of the driving op amp are simultaneously met.
Alternatively, the differential mode of operation with a transformer
coupled input provides the best THD and SFDR performance
over a wide frequency range. This mode of operation should be
considered for the most demanding spectral based applications
that allow ac coupling (e.g., Direct IF to Digital Conversion).
Single-ended operation requires that VINA be ac- or dc-coupled
to the input signal source while VINB of the AD9221/AD9223/
AD9220 can be biased to the appropriate voltage corresponding
to a midscale code transition. Note that signal inversion may be
easily accomplished by transposing VINA and VINB. The rated
specifications for the AD9221/AD9223/AD9220 are character-
ized using single-ended circuitry with input spans of 5 V and
2 V as well as VINB = 2.5 V.
Differential operation requires that VINA and VINB be simulta-
neously driven with two equal signals that are in and out of
phase versions of the input signal. Differential operation of the
AD9221/AD9223/AD9220 offers the following benefits: (1)
Signal swings are smaller and therefore linearity requirements
placed on the input signal source may be easier to achieve, (2)
Signal swings are smaller and therefore may allow the use of op
amps that may otherwise have been constrained by headroom
FREQUENCY– MHz
CMR – dBFigure 11.AD9221/AD9223/AD9220 Input CMR vs.
Input Frequency
limitations, (3) Differential operation minimizes even-order
harmonic products, and (4) Differential operation offers noise
immunity based on the device’s common-mode rejection.
Figure 11 depicts the common-mode rejection of the three devices.
As is typical of most CMOS devices, exceeding the supply limits
will turn on internal parasitic diodes, resulting in transient cur-
rents within the device. Figure 12 shows a simple means of
clamping an ac- or dc-coupled single-ended input with the
addition of two series resistors and two diodes. An optional capaci-
tor is shown for ac-coupled applications. Note that a larger
series resistor could be used to limit the fault current through
D1 and D2 but should be evaluated since it can cause a degrada-
tion in overall performance. A similar clamping circuit could also
be used for each input if a differential input signal is being applied.
Table II.Reference Configuration Summary(Dynamic)
Figure 12.Simple Clamping Circuit
SINGLE-ENDED MODE OF OPERATIONThe AD9221/AD9223/AD9220 can be configured for single-
ended operation using dc or ac coupling. In either case, the
input of the A/D must be driven from an operational amplifier
that will not degrade the A/D’s performance. Because the A/D
operates from a single-supply, it will be necessary to level-shift
ground-based bipolar signals to comply with its input require-
ments. Both dc and ac coupling provide this necessary function,
but each method results in different interface issues that may
influence the system design and performance.
DC COUPLING AND INTERFACE ISSUESMany applications require the analog input signal to be dc-
coupled to the AD9221/AD9223/AD9220. An operational
amplifier can be configured to rescale and level shift the input
signal so that it is compatible with the selected input range of
the A/D. The input range to the A/D should be selected on the
basis of system performance objectives as well as the analog
power supply availability since this will place certain constraints
on the op amp selection.
Many of the new high performance op amps are specified for
only ±5 V operation and have limited input/output swing capa-
bilities. Therefore, the selected input range of the AD9221/
AD9223/AD9220 should be sensitive to the headroom require-
ments of the particular op amp to prevent clipping of the signal.
Also, since the output of a dual supply amplifier can swing
below –0.3 V, clamping its output should be considered in some
applications.
In some applications, it may be advantageous to use an op
amp specified for single-supply 5 V operation since it will
inherently limit its output swing to within the power supply
rails. An amplifier like the AD8041, AD8011, and AD817 are
useful for this purpose. Rail-to-rail output amplifiers such as
the AD8041 allow the AD9221/AD9223/AD9220 to be con-
figured for larger input spans, which improves the noise
performance.
If the application requires the largest input span (i.e., 0 V to
5 V) of the AD9221/AD9223/AD9220, the op amp will require
larger supplies to drive it. Various high speed amplifiers in the
Op Amp Selection Guide of this data sheet can be selected to
accommodate a wide range of supply options. Once again,
clamping the output of the amplifier should be considered for
these applications.
Two dc-coupled op amp circuits using a noninverting and
inverting topology are discussed below. Although not shown,
the noninverting and inverting topologies can be easily config-
ured as part of an antialiasing filter by using a Sallen-Key or
network can be inserted between the op amp’s output and the
AD9221/AD9223/AD9220 input to provide a real pole.
Simple Op Amp BufferIn the simplest case, the input signal to the AD9221/AD9223/
AD9220 will already be biased at levels in accordance with the
selected input range. It is simply necessary to provide an
adequately low source impedance for the VINA and VINB
analog input pins of the A/D. Figure 13 shows the recommended
configuration for a single-ended drive using an op amp. In this
case, the op amp is shown in a noninverting unity gain configu-
ration driving the VINA pin. The internal reference drives the
VINB pin. Note that the addition of a small series resistor of
30 Ω to 50 Ω connected to VINA and VINB will be beneficial
in nearly all cases. Refer to the Analog Input Operation section
for a discussion on resistor selection. Figure 13 shows the
proper connection for a 0 V to 5 V input range. Alternative
single-ended input ranges of 0 V to 2 × VREF can also be real-
ized with the proper configuration of VREF (refer to the Using
the Internal Reference section).
Figure 13.Single-Ended AD9221/AD9223/AD9220
Op Amp Drive Circuit
Op Amp with DC Level ShiftingFigure 14 shows a dc-coupled level shifting circuit employing an
op amp, A1, to sum the input signal with the desired dc offset.
Configuring the op amp in the inverting mode with the given
resistor values results in an ac signal gain of –1. If the signal
inversion is undesirable, interchange the VINA and VINB con-
nections to re-establish the original signal polarity. The dc voltage
at VREF sets the common-mode voltage of the AD9221/AD9223/
AD9220. For example, when VREF = 2.5 V, the output level
from the op amp will also be centered around 2.5 V. The use of
ratio matched, thin-film resistor networks will minimize gain
and offset errors. Also, an optional pull-up resistor, RP, may be
used to reduce the output load on VREF to ±1 mA.
AD9221/AD9223/AD9220
AC COUPLING AND INTERFACE ISSUESFor applications where ac coupling is appropriate, the op amp’s
output can be easily level shifted to the common-mode voltage,
VCM, of the AD9221/AD9223/AD9220 via a coupling capacitor.
This has the advantage of allowing the op amp’s common-mode
level to be symmetrically biased to its midsupply level (i.e.,
(VCC + VEE)/2). Op amps that operate symmetrically with respect
to their power supplies typically provide the best ac performance
as well as the greatest input/output span. Thus, various high
speed/performance amplifiers that are restricted to +5 V/–5 V
operation and/or specified for 5 V single-supply operation can be
easily configured for the 5 V or 2 V input span of the AD9221/
AD9223/AD9220. The best ac distortion performance is achieved
when the A/D is configured for a 2 V input span and common-
mode voltage of 2.5 V. Note that differential transformer coupling,
which is another form of ac coupling, should be considered for
optimum ac performance.
Simple AC InterfaceFigure 15 shows a typical example of an ac-coupled, single-ended
configuration. The bias voltage shifts the bipolar, ground-refer-
enced input signal to approximately VREF. The value for C1
and C2 will depend on the size of the resistor, R. The capacitors,
C1 and C2, are typically a 0.1 µF ceramic and 10 µF tanta-
lum capacitor in parallel to achieve a low cutoff frequency
while maintaining a low impedance over a wide frequency
range. The combination of the capacitor and the resistor form a
high-pass filter with a high-pass –3 dB frequency determined
by the equation,
The low impedance VREF voltage source both biases the VINB
input and provides the bias voltage for the VINA input. Figure 15
shows the VREF configured for 2.5 V; thus the input range
Figure 15.AC-Coupled Input
of the A/D is 0 V to 5 V. Other input ranges could be selected
by changing VREF, but the A/D’s distortion performance will
degrade slightly as the input common-mode voltage deviates
from its optimum level of 2.5 V.
Alternative AC InterfaceFigure 16 shows a flexible ac-coupled circuit that can be config-
ured for different input spans. Since the common-mode voltage
of VINA and VINB are biased to midsupply independent of
VREF, VREF can be pin-strapped or reconfigured to achieve
input spans between 2 V and 5 V p-p. The AD9221/AD9223/
AD9220’s CMRR along with the symmetrical coupling R-C
networks will reject both power supply variations and noise. The
in parallel to achieve a low cutoff frequency while maintaining a
low impedance over a wide frequency range. RS isolates the
buffer amplifier from the A/D input. The optimum performance
is achieved when VINA and VINB are driven via «Immetrical
networks. The f–3 dB point can be approximated by the equation,
Figure 16.AC-Coupled Input-Flexible Input Span,
VCM = 2 V
Op Amp Selection GuideOp amp selection for the AD9221/AD9223/AD9220 is highly
dependent on a particular application. In general, the performance
requirements of any given application can be characterized by
either time domain or frequency domain parameters. In either
case, one should carefully select an op amp that preserves the
performance of the A/D. This task becomes challenging when
one considers the AD9221/AD9223/AD9220’s high perfor-
mance capabilities coupled with other extraneous system level
requirements such as power consumption and cost.
The ability to select the optimal op amp may be further compli-
cated by either limited power supply availability and/or limited
acceptable supplies for a desired op amp. Newer, high perfor-
mance op amps typically have input and output range limitations
in accordance with their lower supply voltages. As a result, some
op amps will be more appropriate in systems where ac-coupling
is allowable. When dc-coupling is required, op amps without
headroom constraints, such as rail-to-rail op amps or ones
where larger supplies can be used, should be considered. The
following section describes some op amps currently available
from Analog Devices. The system designer is always encouraged
to contact the factory or local sales office to be updated on Analog
Devices’ latest amplifier product offerings. Highlights of the
areas where the op amps excel and where they may limit the
performance of the AD9221/AD9223/AD9220 is also included.
AD817:50 MHz Unity GBW, 70 ns Settling to 0.01%, +5 V
to ±15 V Supplies
Best Applications: Sample Rates < 7 MSPS, Low
Noise, 5 V p-p Input Range
Limits: THD above 100 kHz
AD826:Dual Version of AD817
Best Applications: Differential and/or Low Imped-
ance Input
Drivers, Low Noise
Limits: THD above 100 kHz
AD818:130 MHz @ G = +2 BW, 80 ns Settling to 0.01%,
