AD8564ARU ,Quad 7 ns Single Supply ComparatorSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS2Package Type UnitsJA J ..
AD8565AKSZ-REEL7 , 16 V Rail-to-Rail Operational Amplifiers
AD8566ARM ,16 V Rail-to-Rail Operational Amplifiersapplications.COMThe AD8565, AD8566, and AD8567 are specified over the–40°Cto +85°C temperature rang ..
AD8566ARM-REEL ,16 V Rail-to-Rail Operational Dual AmplifierSpecifications subject to change without notice.REV. C–2–AD8565/AD8566/AD8567ABSOLUTE MAXIMUM RATIN ..
AD8566ARM-REEL ,16 V Rail-to-Rail Operational Dual AmplifierCHARACTERISTICSOutput Voltage High V I = 100 µAV – 0.005 VOH L SV = 16 V, I = 5 mA 15.85 15.95 VS L ..
AD8566ARMZ-R2 , 16 V Rail-to-Rail Operational Amplifiers
ADR5045ARTZ-REEL7 , Precision Micropower Shunt Mode Voltage References
ADR5045BKSZ-REEL7 , Precision Micropower Shunt Mode Voltage References
ADR510ART-R2 ,1.0 V Precision Low Noise Shunt Voltage ReferenceSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS* 1 2Package Type UnitJ ..
ADR510ART-REEL7 ,1.0 V Precision Low Noise Shunt Voltage ReferenceCHARACTERISTICS (I = 100 A to 10 mA @ T = 25C, unless otherwise noted.)IN AParameter Symbol Condi ..
ADR510ART-REEL7 ,1.0 V Precision Low Noise Shunt Voltage Referenceapplications.VSRI + IL Q BIASILV = 1.0VOUTIADR510 QCOUT(OPTIONAL)V – VS OUTR = BIASI + IL QFigure ..
ADR512ART-REEL7 ,1.2 V Precision Low Noise Shunt Voltage ReferenceSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS* 1 2Package Type UnitJ ..
AD8564AR-AD8564ARU
Quad 7 ns Single Supply Comparator
REV.A
Quad 7 ns
Single Supply Comparator
PIN CONFIGURATIONSFEATURES
+5 V Single-Supply Operation
7 ns Propagation Delay
Low Power
Separate Input and Output Sections
TTL and CMOS Logic Compatible Outputs
Wide Output Swing
TSSOP, SOIC and PDIP Packages
APPLICATIONS
High Speed Timing
Line Receivers
Data Communications
High Speed V-to-F Converters
Battery Operated Instrumentation
High Speed Sampling Systems
Window Comparators
Read Channel Detection
PCMCIA Cards
Upgrade for MAX901 Designs
GENERAL DESCRIPTIONThe AD8564 is quad 7 ns comparator with separate input and
output supplies, thus enabling the input stage to be operated
from ±5 V dual supplies or a +5 V single supply while maintain-
ing a CMOS/TTL-compatible output.
Fast 7 ns propagation delay makes the AD8564 a good choice
for timing circuits and line receivers. Independent analog and
digital supplies provide excellent protection from supply pin
interaction. The AD8564 is pin compatible with the MAX901,
and has lower supply currents.
All four comparators have similar propagation delays. The
propagation delay for rising and falling signals is similar, and
tracks over temperature and voltage. These characteristics
make the AD8564 a good choice for high speed timing and data
communications circuits. For a similar dual comparator with a
latch function, please see the AD8598 data sheet. For a similar
single comparator with latch function, please see the AD8561
data sheet.
The AD8564 is specified over the industrial (–40°C to +85°C)
temperature range. The quad AD8564 is available in the 16-
lead plastic DIP, narrow SO-16 surface mount, and 16-lead
TSSOP packages.
16-Lead Narrow Body SO
(S Suffix)
R-16A
16-Lead TSSOP
(RU-Suffix)
RU-16
16-Lead Epoxy DIP
(P Suffix)
N-16
AD8564–SPECIFICATIONS
ELECTRICAL SPECIFICATIONSNOTESGuaranteed by design.
Specifications subject to change without notice.
(@ V+ANA = V+DIG = +5.0 V, V–ANA = 0 V, TA = +25�C unless otherwise noted)
ELECTRICAL SPECIFICATIONS
(@ V+ANA = V+DIG = +5.0 V, V–ANA = –5 V, TA = +25�C unless otherwise noted)
AD8564NOTESGuaranteed by design.
Specifications subject to change without notice.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8564 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGSTotal Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . .+14 V
Digital Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .+17 V
Analog Positive Supply–Digital Positive Supply . . . . .–600 mV
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .±8 V
Output Short-Circuit Duration to GND . . . . . . . . .Indefinite
Storage Temperature Range
N, R, RU Package . . . . . . . . . . . . . . . . . .–65°C to +150°C
Operating Temperature Range . . . . . . . . . . .–40°C to +85°C
Junction Temperature Range
N, R, RU Package . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range (Soldering, 10 sec) . . . . . . .+300°C
NOTESThe analog input voltage is equal to ±7 V or the analog supply voltage, whichever
is less.θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for, P-DIP, and θJA is specified for device soldered in circuit board for SOIC and
TSSOP packages.
ORDERING GUIDE
AD8564
–Typical Performance CharacteristicsFigure 1.Input Offset Voltage vs.
Temperature
Figure 4.Input Offset Voltage
Figure 7.Output Low Voltage, VOL
vs. Sink Current
Figure 2.Input Bias Current vs.
Temperature
Figure 5.Propagation Delay, tPDHL/
tPDLH vs. Temperature
Figure 8.I+ANA: Analog Supply Cur-
rent/Comparator vs. Supply Voltage
INPUT COMMON-MODE VOLTAGE – V
INPUT BIAS CURRENT
–7.5–55–2.502.5Figure 3.Input Bias Current vs. Input
Common-Mode Voltage
Figure 6.Output High Voltage, VOH
vs. Source Current
Figure 9.I–ANA: Analog Supply Cur-
rent/Comparator vs. Supply Voltage
(V+ ANA = V+DIG = +5 V, V– ANA = 0 V, TA = +25�C unless
otherwise noted)
Figure 10.I+DIG: Digital Supply Cur-
rent/Comparator vs. Supply Voltage
Figure 13.I+DIG: Digital Supply Current/
Comparator vs. Temperature
APPLICATIONS
OPTIMIZING HIGH SPEED PERFORMANCEAs with any high speed comparator or amplifier, proper design
and layout techniques should be used to ensure optimal perfor-
mance from the AD8564. The performance limits of high speed
circuitry can easily be a result of stray capacitance, improper
ground impedance or other layout issues.
Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
AD8564. Source resistance in combination with equivalent
input capacitance could cause a lagged response at the input,
thus delaying the output. The input capacitance of the AD8564
in combination with stray capacitance from an input pin to
ground could result in several picofarads of equivalent capaci-
tance. A combination of 3 kΩ source resistance and 5 pF of
input capacitance yields a time constant of 15 ns, which is
slower than the 5 ns capability of the AD8564. Source imped-
ances should be less than 1 kΩ for the best performance.
It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 µF electrolytic bypass
power supply pins to ground. These capacitors act as a charge
reservoir for the device during high frequency switching.
A ground plane is recommended for proper high speed perfor-
mance. This can be created by using a continuous conductive
plane over the surface of the circuit board, only allowing breaks
in the plane for necessary current paths. The ground plane
provides a low inductance ground, eliminating any potential
differences at different ground points throughout the circuit
board caused from “ground bounce.” A proper ground plane
also minimizes the effects of stray capacitance on the circuit
board.
OUTPUT LOADING CONSIDERATIONSThe AD8564 output can deliver up to 40 mA of output current
without any significant increase in propagation delay. The out-
put of the device should not be connected to more than twenty
(20) TTL input logic gates, or drive a load resistance less than
100 Ω.
To ensure the best performance from the AD8564 it is impor-
tant to minimize capacitive loading of the output of the device.
Figure 12.I–ANA: Analog Supply Cur-
rent/Comparator vs. Temperature
Figure 11.I+ANA: Analog Supply Cur-
rent/Comparator vs. Temperature
AD8564
INPUT STAGE AND BIAS CURRENTSThe AD8564 uses a PNP differential input stage which enables
the input common-mode range to extend all the way from the
negative supply rail to within 2.2 V of the positive supply rail.
The input common-mode voltage can be found as the average of
the voltage at the two inputs of the device. To ensure the fastest
response time, care should be taken to not allow the input
common-mode voltage to exceed this voltage.
The input bias current for the AD8564 is 4 µA. As with any
PNP differential input stage, this bias current will go to zero on
an input that is high and will double on an input that is low.
Care should be taken in choosing resistor values to be connected
to the inputs as large resistors could cause significant voltage
drops due to the input bias current.
The input capacitance for the AD8564 is typically 3 pF. This is
measured by inserting a kΩ source resistance to the input and
measuring the change in propagation delay.
USING HYSTERESISHysteresis can easily be added to a comparator through the
addition of positive feedback. Adding hysteresis to a comparator
offers an advantage in noisy environments where it is not desir-
able for the output to toggle between states when the input
signal is near the switching threshold. Figure 14 shows a method
for configuring the AD8564 with hysteresis.
Figure 14.Configuring the AD8564 with Hysteresis
The input signal is connected directly to the inverting input of
the comparator. The output is fed back to the noninverting
input through R2 and R1. The ratio of R1 to R1 + R2 estab-
lishes the width of the hysteresis window with VREF setting the
center of the window, or the average switching voltage. The
output will switch high when the input voltage is greater than
VHI and will not switch low again until the input voltage is less
than VLO as given in Equation 1:
(1)
Where V+ is the positive supply voltage.
The capacitor CF can also be added to introduce a pole into the
feedback network. This has the effect of increasing the amount
of hysteresis at high frequencies. This can be useful when com-
paring a relatively slow signal in a high frequency noise environ-
ment. At frequencies greater than fP =
window approaches VHI = V+ – 1 V and VLO = 0 V. At frequen-
cies less than fP the threshold voltages remain as in Equation 1.
