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ADP3300ARTZ-3.3RL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear RegulatorGENERAL DESCRIPTION +R1C1C2330kThe ADP3300 is a member of the ADP330x family of precision 0.47F0. ..
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ADP3300ARTZ-5REEL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear RegulatorSpecifications subject to change without notice.–2– REV. BADP3300ABSOLUTE MAXIMUM RATINGS* PIN FUNC ..
ADP3300ARTZ-5-REEL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear Regulator®High Accuracy anyCAPa50 mA Low Dropout Linear RegulatorADP3300
AD8330ARQ
Low Cost DC-150 MHz Variable Gain Amplifier
REV.A
Low Cost DC-150 MHz
Variable Gain Amplifier*.Patent No. 5,969,657; other patents pending.
FUNCTIONAL BLOCK DIAGRAMFigure 1.AC Response over the Extended Gain Range
FEATURES
Fully Differential Signal Path
May also be Used with Single-Sided Signals
Inputs from 0.3 mV to 1 V rms, Rail-Rail Outputs
Differential RIN = 1 k�; ROUT (Each Output) 75 �
Automatic Offset Compensation (Optional)
Linear-in-dB and Linear-in-Magnitude Gain Modes
0 dB to 50 dB, for 0V < VDBS < 1.5V (30 mV/dB)
Inverted Gain Mode: 50 dB to 0 dB at –30 mV/dB�0.03 to �10 Nominal Gain for 15 mV < VMAG < 5 V
Constant Bandwidth: 150 MHz at All Gains
Low Noise: 5 nV/√Hz typical at Maximum Gain
Low Distortion: ≤–62 dBc Typ
Low Power: 20 mA Typ at VS of 2.7V – 6 V
Available in Space Saving 3 � 3 LFCSP Package
APPLICATIONS
Pre-ADC Signal Conditioning� Cable Driving Adjust
AGC Amplifiers
GENERAL DESCRIPTIONThe AD8330 is a wideband variable-gain amplifier for use in
applications requiring a fully differential signal path, low noise, well-
defined gain, and moderately low distortion, from dc to 150MHz.
The input pins can also be driven from a single ended source. The
peak differential input is ±2V, allowing sinewave operation at
1V rms with generous headroom. The output pins can optionally
drive single-sided loads and each swing essentially rail-to-rail.
The differential output resistance is 150Ω. The output swing is
a linear function of the voltage applied to the VMAG pin, which
internally defaults to 0.5 V, to provide a peak output of ±2 V.
This may be raised to 10 V p-p, limited by the supply voltage.
The basic gain function is linear-in-dB, controlled by the voltage
applied to pin VDBS. The gain ranges from 0 dB to 50 dB for
control voltages between 0V and 1.5 V—a slope of 30 mV dB.
The gain linearity is typically within ±0.1 dB. By changing the
logic level on pin MODE, the gain will decrease over the same
range, with opposite slope. A second gain control port is provided
at pin VMAG and allows the user to vary the numeric gain from a
factor of 0.03 to 10. All the parameters of the AD8330 have low
sensitivities to temperature and supply voltages.
Using VMAG, the basic 0 dB to 50 dB range can be repositioned to any
value from 20 dB higher (that is, 20 dB to 70 dB) to at least 30dB
lower (that is, –30dB to +20dB) to suit the application, providing
an unprecedented gain range of over 100 dB. A unique aspect of
the AD8330 is that its bandwidth and pulse response are essentially
constant for all gains, not only over the basic 50dB linear-in-dB
range, but also when using the linear-in-magnitude function. The
exceptional stability of the HF response over the gain range is of
particular value in those VGA applications where it is essential
to maintain accurate gain law-conformance at high frequencies.
An external capacitor at pin OFST sets the high-pass corner of an
offset reduction loop, whose frequency may be as low as 5Hz.
When this pin is grounded, the signal path becomes dc-coupled.
When used to drive an ADC, an external common-mode control
voltage at pin CNTR can be driven to within 0.5V of either
ground or VS to accommodate a wide variety of requirements. By
default, the two outputs are positioned at the mid point of the
supply, VS/2. Other features, such as two levels of power-down
(fully off and a hibernate mode), further extend the practical
value of this exceptionally versatile VGA.
The AD8330 is available in a 16-lead LFCSP and 16-lead QSOP
AD8330–SPECIFICATIONS
(VS = 5 V, TA = 25�C, CL = 12 pF on OPHI and OPLO, RL = 0/C, VDBS = 0.75 V, VMODE = HI,
VMAG = 0/C, VOFST = 0 V, Differential Operation, unless otherwise noted.)OUTPUT INTERFACE
DECIBEL GAIN CONTROL
LINEAR GAIN INTERFACE
AD8330NOTESThe use of an input common-mode voltage significantly different than the internally set value is not recommended due to its effect on noise performance.
See Figure 13.See Typical Performance Characteristics for more detailed information on distortion in a variety of operating conditions.For minimum sized coupling capacitors.
AD8330
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 V
Power Dissipation
RQ Package2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.62 W
CP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.67 W
Input Voltage at Any Pin . . . . . . . . . . . . . . . . . . .VS + 200 mV
Storage Temperature . . . . . . . . . . . . . . . . . . .–65∞C to +105∞C
Operating Temperature Range . . . . . . . . . . . .–40∞C to +85∞C
Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . .300∞C
NOTESStresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Four-Layer JEDEC Board (252P).
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8330 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTIONS
16-Lead LFCSP
16-Lead QSOP
16-Lead QSOP
16-Lead LFCSPVSPIINHIINLOMODE
VPSO
OPHI
OPLO
CMOP
ENBLOFSTVPOSCNTR
VDBS
CMGN
COMM
VMA
AD8330
TOP VIEW
(Not to Scale)
AD8330–Typical Performance CharacteristicsTPC 1. Gain vs. VDBS
TPC 2. Linear Gain Multiplication Factor vs. VMAG
TPC 3. Gain Linearity Error Normalized at 25°C vs.
TPC 4. Gain Error vs. VDBS at Various Frequencies
TPC 5. Gain Slope Histogram
TPC 6. Frequency Response in 10 dB Steps for
VS = 5 V, TA = 25�C, CL = 12 pF, VDBS = 0.75 V, VMODE = High (or O/C) VMAG = O/C, RL = O/C, VOFST = 0, Differential Operation, unless otherwise stated.
TPC 7. Frequency Response for Various Values of VMAG
TPC 8. Group Delay vs. Frequency
TPC 9. Differential Output Offset vs. VDBS for
Three Temperatures, for a Representative Part
TPC 10. Differential Input Offset Histogram
TPC 11. Output Balance Error vs. Frequency forRepresentative Part
TPC 12. Output Impedance vs. Frequency
AD8330TPC 13. CMRR vs. Frequency
TPC 14. Output Referred Noise vs. VDBS for
Three Temperatures
TPC 15. Output Referred Noise vs. VMAG
TPC 16. Output Referred Noise vs. VMAG
TPC 17. Input Referred Noise vs. VDBS for
Three Temperatures
TPC 18. Input Referred Noise vs. VDBS for Three
Values of VMAG
TPC 19.Input Referred Noise vs. Frequency
TPC 20.Harmonic Distortion vs. Frequency
TPC 21.Harmonic Distortion vs. CLOAD
TPC 22.Harmonic Distortion vs.
VOUT-DIFFERENTIAL VMAG = 0.5 V
TPC 23.Harmonic Distortion vs.
VOUT-DIFFERENTIAL VMAG = 2.0 V
TPC 24.Harmonic Distortion vs. VDBS
AD8330TPC 25. Input Voltage 1 dBV vs. VDBS
TPC 26. Output Voltage 1 dB vs. VMAG
TPC 27. IM3 Distortion vs. Frequency
TPC 28. Output IP3 vs. VDBS
TPC 29. Output IP3 vs. VMAG
TPC 30. Full-Scale Transient Response, VDBS = 0 V
TPC 31.Full-Scale Transient Response,
VDBS=0.75 V, f=1 MHz, VOUT=2 V p-p
TPC 32.Full-Scale Transient Response,
VDBS = 1.5 V, f=1 MHz, VOUT=2 V p-p
TPC 33.Transient Response vs. for Various Load
Capacitances, G = 25 dB
TPC 34.VDBS Interface Response
Top: VDBS, Bottom: VOUT
TPC 35.VMAG Interface Response
Top: VMAG, Bottom: VOUT
TPC 36.Transient Response vs. VMAG
AD8330TPC 37.Overdrive Response, VDBS = 1.5 V,
VMAG = 0.5 V, 18.5 dB Overdrive
TPC 38.ENBL Interface Response. Top: VENBL;
Bottom: VOUT, f = 10 MHz
TPC 39.PSRR vs. Frequency
TPC 40.Supply Current vs. VDBS at Three Temperatures
TPC 41.CNTR Transient Response
Top: Input to CNTR; Bottom, VOUT Single Ended
CIRCUIT DESCRIPTIONMany monolithic variable-gain amplifiers use techniques that share
common principles that are broadly classified as translinear, a
term referring to circuit cells whose functions depend directly on
the very predictable properties of bipolar junction transistors,
notably the linear dependence of their transconductance on collec-
tor current. Since the discovery of these cells in 1967, and their
commercial exploitation in products developed during the early 1970s,
accurate wide bandwidth analog multipliers, dividers, and variable-
gain amplifiers have invariably employed translinear principles.
While these techniques are well understood, the realization of a
high performance variable-gain amplifier (VGA) requires special
technologies and attention to many subtle details in its design.
The AD8330 is fabricated on a proprietary silicon-on-insulator,
complementary bipolar IC process and draws on decades of
experience in developing many leading-edge products using trans-
linear principles to provide an unprecedented level of versatility.
Figure 2 shows a basic representative cell comprising just four
transistors. This, or a very closely related form, is at the heart of most
translinear multipliers, dividers, and VGAs. The key concepts
are as follows: First, the ratio of the currents in the left-hand and
right-hand pairs of transistors are identical; this is represented
by the modulation factor, x, which may have values between –1
and +1. Second, the input signal is arranged to modulate the fixed
tail current ID to cause the variable value of x introduced in the
left-hand pair to be replicated in the right-hand pair, and thus
generate the output by modulating its nominally fixed tail current
IN. Third, the current-gain of this cell is very exactly G = IN/ID
over many decades of variable bias current. In practice, the
realization of the full potential of this circuit involves many other
factors, but these three elementary ideas remain essential.
By varying IN, the overall function is that of a two-quadrant
analog multiplier, exhibiting a linear relationship to both the signal
modulation factor x and this numerator current. On the other
hand, by varying ID, a two-quadrant analog divider is realized,
having a hyperbolic gain function with respect to the input
factor x, controlled by this denominator current. The AD8330
exploits both modes of operation. However, since a hyperbolic
gain function is generally of less value than one in which the
decibel gain is a linear function of a control input, a special interface
is included to provide either increasing or decreasing exponential
control of ID.
Figure 2.The Basic Core of the AD8330
Figure 3.Block Schematic of the AD8330
Overall StructureFigure 3 shows a block schematic of the AD8330 in which the key
sections are located. More detailed discussions of its structure
and features are provided later; this figure provides a general
overview of its capabilities.
The VGA core contains a much elaborated version of the cell shown
in Figure 2. The current called ID is controlled exponentially
(linear in decibels) through the decibel gain interface at the pin
VDBS and its local common CMGN. The gain span (that is,
the decibel difference between maximum and minimum values)
provided by this control function is slightly more than 50 dB.
The absolute gain from input to output is a function of source
and load impedance and also depends on the voltage on a second
gain-control pin, VMAG, as will be explained in a moment.
Normal Operating ConditionsTo minimize confusion, we define these normal operating condi-
tions: the input pins are voltage driven (the source impedance is
assumed to be zero); the output pins are open circuited (the load
impedance is assumed to be infinite); pin VMAG is unconnected,
which sets up the output bias current (IN in the four-transistor gain
cell) to its nominal value; pin CMGN is grounded; and MODE
is either tied to a logic high or left unconnected, to set the UP
gain mode. The effects of other operating conditions can then be
considered separately.
Throughout this data sheet, the end-to-end voltage gain for the
normal operating conditions will be referred to as the Basic
Gain. Under these conditions, it runs from 0 dB when VDBS = 0
(where this voltage is more exactly measured with reference to
pin CMGN, which may not necessarily be tied to ground) up to
50 dB for VDBS = 1.5 V. The gain does not “fold-over” when
the VDBS pin is driven below ground or above its nominal full-
scale value.
The input is accepted at the differential port INHI/INLO. These
pins are internally biased to roughly the midpoint of the supply
VS (it is actually ~2.75 V for VS = 5 V, VDBS = 0, and 1.5V for VS
= 3 V), but the AD8330 is able to accept a forced common-
mode value, from zero to VS, with certain limitations. This interface
provides good common-mode rejection up to high frequencies
(see TPC 13) and thus can be driven in either a single-sided or
AD8330The pin-to-pin input resistance is specified as 950 Ω ±20%.
The driving-point impedance of the signal source may range
from zero up to values considerably in excess of this resis-
tance, with a corresponding variation in noise figure (see
Figure 10). In most cases, the input will be coupled via two
capacitors, chosen to provide adequate low frequency trans-
mission. This results in the minimum input noise, which is
increased when some other common-mode voltage is forced
onto these pins, as explained later. The short circuit, input-
referred noise at maximum gain is approximately 5nV/√Hz.
The output pins OPHI/OPLO operate at a common-mode
voltage at the midpoint of the supply, VS/2, within a few millivolts.
This ensures that an analog-to-digital converter (ADC) attached
to these outputs operates within the often narrow range permit-
ted by their design. When a common-mode voltage other than VS/2
is required at this interface, it can easily be forced by applying an
externally provided voltage to the output centering pin, CNTR.
This voltage may run from zero to the full supply, though it
must be noted that the use of such extreme values would
leave only a small range for the differential output signal swing.
The differential impedance measured between OPHI and
OPLO is 150 Ω ±20%. It follows that both the gain and the
full-scale voltage swing will depend on the load impedance;
both are nominally halved when this is also 150 Ω. A fixed-
impedance output interface, rather than an op amp style
voltage-mode output, is preferable in high speed applications
since the effects of complex reactive loads on the gain and
phase can be better controlled. The top end of the AD8330’s
ac response is optimally flat for a 12pF load on each pin, but
this is not critical and the system will remain stable for any
value of load capacitance including zero.
Another useful feature of this VGA in connection with the driving
of an ADC is that the peak output magnitude can be precisely
controlled by the voltage on pin VMAG. Usually, this voltage is
internally preset to 500 mV, and the peak differential, unloaded
output swing is ±2 V ±3%. However, any voltage from zero to
at least 5 V can be applied to this pin to alter the peak output in
an exactly proportional way. Since either output pin can swing
“rail to rail,” which in practice means down to at least 0.35V
and to within the same voltage below the supply, the peak-to-peak
output between these pins can be as high as 10 V using VS = 6V.
Linear-in-dB Gain Control (VDBS)A gain control law that is linear in decibels is frequently claimed
for VGAs based more loosely on these principles. However, closer
inspection reveals that their conformance to this ideal gain func-
tion is poor, usually only an approximation over part of the gain
range. Furthermore, the calibration (so many decibels per volt)
is invariably left unspecified, and the resulting gain often varies
wildly with temperature. All Analog Devices VGAs featuring a
linear-in-dB gain law, such as the X-AMP™ family, provide exact,
constant gain scaling over the fully specified gain range, and the
deviation from the ideal response is within a small fraction of a dB.
For the AD8330, the scaling of both its gain interfaces is substan-
tially independent of process, supply voltage, or temperature.
The Basic Gain, GB, is simply:(1)
where VDBS is in volts. Alternatively, this can be expressed as a
numerical gain magnitude:(2)
As discussed later, the gain may be increased or decreased by
changing the voltage VMAG applied to the VMAG pin. The internally
set default value of 500 mV is derived from the same band gap
reference that determines the decibel scaling. The tolerance on this
voltage, and mismatches in certain on-chip resistors, cause small
gain errors (see Specifications). While not all applications of VGAs
demand accurate gain calibration, there are many situations in which
it will be a valuable asset, for example, in reducing design tolerances.
Figure 4 shows the core circuit in somewhat more detail. The
range and scaling of VDBS is independent of the supply voltage,
and the gain-control pin, VDBS, presents a high incremental input
resistance (~100 MΩ) with a low bias current (~100 nA), making
the AD8330 easy to drive from a variety of gain-control sources.
Inversion of the Gain SlopeThe AD8330 supports many new features that further extend
the versatility of this VGA in wide bandwidth, gain-control sys-
tems. For example, the logic pin MODE allows the slope of the
gain function to be inverted, so that the basic gain starts at +50 dB
for a gain voltage VDBS of zero and runs down to 0 dB when this
voltage is at its maximum specified value of 1.5 V. The basic
forms of these two gain control modes are shown in Figure5.
