AD8197B Fast Delivery |IC PHOENIX CO.,LIMITED

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AD8197B
4:1 HDMI/DVI Switch with Equalization
4:1 HDMI/DVI Switch with EqualizationFEATURES
4 inputs, 1 output HDMI/DVI links
Enables HDMI 1.3-compliant receiver
Pin-to-pin compatible with the AD8197A
4 TMDS channels per link
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Equalized inputs allow use of long HDMI cables
(20 meters at 2.25 Gbps)
Fully buffered unidirectional inputs/outputs
Per input switchable, 50 Ω on-chip terminations
Switchable output 50 Ω on-chip terminations
Pre-emphasized outputs
Low added jitter
Single-supply operation (3.3 V)
4 auxiliary channels per link
Bidirectional unbuffered inputs/outputs
Flexible supply operation (3.3 V to 5 V)
HDCP standard compatible
Allows switching of DDC bus and 2 additional signals
Output disable feature
Reduced power dissipation
Removable output termination
Allows building of larger arrays
Two AD8197Bs support HDMI/DVI dual link
Standards compatible: HDMI receiver, HDCP, DVI
Serial (I2C slave) and parallel control interface
100-lead, 14 mm × 14 mm LQFP, Pb-free package
APPLICATIONS
Multiple input displays
Projectors
A/V receivers
Set-top boxes
Advanced television (HDTV) sets
TYPICAL APPLICATION
DVD PLAYER
GAME CONSOLE
MEDIA CENTER
HDTV SET
Figure 1. Typical HDTV Application
FUNCTIONAL BLOCK DIAGRAM
AVCC
DVCC
AMUXVCC
AVEE
DVEE
VTTO
OP[3:0]
ON[3:0]
I2C_SDAI2C_SCLI2C_ADDR[2:0]
VTTI
VTTI
IP_A[3:0]IN_A[3:0]
IP_B[3:0]IN_B[3:0]
IP_C[3:0]IN_C[3:0]
IP_D[3:0]IN_D[3:0]
AUX_C[3:0]
AUX_B[3:0]
AUX_A[3:0]
AUX_D[3:0]SERIALPARALLEL
CH[
RESET
Figure 2.
GENERAL DESCRIPTION
The AD8197B is an HDMI™/DVI switch featuring equalized
TMDS® inputs and pre-emphasized TMDS outputs, ideal for
systems with long cable runs. The AD8197B offers individual
control of the on/off state of the TMDS input termination
resistors via I2C® control. Outputs can be set to a high
impedance state to reduce the power dissipation and/or to allow
the construction of larger arrays using the wire-OR technique.
The AD8197B is provided in a 100-lead LQFP, Pb-free, surface-
mount package, specified to operate over the −40°C to +85°C
temperature range.
PRODUCT HIGHLIGHTS
1. Supports data rates up to 2.25 Gbps, enabling 1080p deep
color (12-bit color) HDMI formats and greater than UXGA
(1600 × 1200) DVI resolutions.
2. Input cable equalizer enables use of long cables at the input
(more than 20 meters of 24 AWG cable at 2.25 Gbps).
3. Auxiliary switch routes a DDC bus and two additional signals
for a single-chip, HDMI 1.3 receive-compliant solution.
TABLE OF CONTENTS
Features..............................................................................................1
Applications.......................................................................................1
Typical Application...........................................................................1
Functional Block Diagram..............................................................1
General Description.........................................................................1
Product Highlights...........................................................................1
Revision History...............................................................................2
Specifications.....................................................................................3
Absolute Maximum Ratings............................................................5
Thermal Resistance......................................................................5
Maximum Power Dissipation.....................................................5
ESD Caution..................................................................................5
Pin Configuration and Function Descriptions.............................6
Typical Performance Characteristics.............................................9
Theory of Operation......................................................................13
Introduction................................................................................13
Input Channels............................................................................13
Output Channels........................................................................13
Auxiliary Switch..........................................................................14
Serial Control Interface..................................................................15
Reset.............................................................................................15
Write Procedure..........................................................................15
Read Procedure...........................................................................16
Switching/Update Delay............................................................16
Parallel Control Interface..............................................................17
Serial Interface Configuration Registers.....................................18
High Speed Device Modes Register.........................................19
Auxiliary Device Modes Register.............................................19
Receiver Settings Register.........................................................19
Input Termination Select Register 1 and Register 2..............19
Receive Equalizer Register 1 and Register 2...........................19
Transmitter Settings Register....................................................20
Parallel Interface Configuration Registers..................................21
High Speed Device Modes Register.........................................22
Auxiliary Device Modes Register.............................................22
Input Termination Resistor Control Register 1
and Register 2..............................................................................22
Receive Equalizer Register 1 and Register 2...........................22
Transmitter Settings Register....................................................22
Application Information................................................................23
Pinout...........................................................................................23
Cable Lengths and Equalization...............................................23
PCB Layout Guidelines..............................................................24
Outline Dimensions.......................................................................28
Ordering Guide..........................................................................28
REVISION HISTORY
1/08—Revision 0: Initial Version
SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
Table 1.
1 Differential interpair skew is measured between the TMDS pairs of a single link. AD8197B output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.
3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. Typical value assumes only the selected HDMI/DVI link is active with nominal signal swings and that the unselected HDMI/DVI links are deactivated. Minimum and
maximum limits are measured at the respective extremes of input termination resistance and input voltage swing. The AD8197B is an I2C slave and its serial control interface is based on the 3.3 V I2C bus specification.
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions: a device soldered
in a 4-layer JEDEC circuit board for surface-mount packages.
θJC is specified for no airflow.
Table 3. Thermal Resistance
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8197B
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure. To ensure proper operation, it
is necessary to observe the maximum power rating as determined
by the coefficients in Table 3.
ESD CAUTION
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AUX
_A0
AUX
_A1
AUX
_A2
AUX
_A3
AUX
_B0
AUX
_B1
AUX
_B2
AUX
_B3
AUX
_CO
AUX
_CO
AUX
_CO
AUX
_CO
AUX
_C0
AUX
_C1
AUX
_C2
AUX
_C3
AUX
_D0
AUX
_D1
AUX
_D2
AUX
_D3
C_ADDR
DDR1
C_ADDR2
VEE
PP_
_CH1IN_B0IP_B0AVEEVTTIIP_B1IN_B1AVCCIN_B2IP_B2AVEEIP_B3AVCCIN_A0IP_A0AVEEIN_A1IP_A1VTTIIN_A2IP_A2AVCCIN_A3IP_A3AVEEIN_B3IP_C3
AVCCIN_C3AVEEVTTIIN_C2IP_C2IP_C1IN_C1AVEEIN_C0AVCCIP_D3IN_D3AVEEIP_D2IN_D2VTTIIP_D1IN_D1AVCCIP_D0IN_D0AVEEIP_C0
PP_
PP_
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions

HS = high speed, LS = low speed, I = input, O = output.
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless
otherwise noted.
REFERENCE EYE DIAGRAM AT TP1
SMA COAX CABLE
HDMI CABLE
TP1TP2TP3
Figure 4. Test Circuit Diagram for Rx Eye Diagram
0.125UI/DIV AT 2.25Gbps
Figure 5. Rx Eye Diagram at TP2 (Cable = 2 meters, 30 AWG)
0.125UI/DIV AT 2.25Gbps
Figure 6. Rx Eye Diagram at TP2 (Cable = 20 meters, 24 AWG)
0.125UI/DIV AT 2.25Gbps
Figure 7. Rx Eye Diagram at TP3, EQ = 6 dB (Cable = 2 meters, 30 AWG)
0.125UI/DIV AT 2.25Gbps
Figure 8. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 20 meters, 24 AWG)
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless
otherwise noted.
REFERENCE EYE DIAGRAM AT TP1
SMA COAX CABLE
HDMI CABLE
TP1TP2TP3
Figure 9. Test Circuit Diagram for Tx Eye Diagrams
0.125UI/DIV AT 2.25Gbps
Figure 10. Tx Eye Diagram at TP2, PE = 2 dB
0.125UI/DIV AT 2.25Gbps
Figure 11. Tx Eye Diagram at TP2, PE = 6 dB
0.125UI/DIV AT 2.25Gbps
Figure 12. Tx Eye Diagram at TP3, PE = 2 dB (Cable = 2 meters, 30 AWG)
0.125UI/DIV AT 2.25Gbps
Figure 13. Tx Diagram at TP3, PE = 6 dB (Cable = 10 meters, 28 AWG)
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless
otherwise noted.
HDMI CABLE LENGTH (m)
ITT
(U
5101520
DATA RATE (Gbps)
Figure 14. Jitter vs. Input Cable Length (See Figure 4 for Test Setup) 02.4
0.20.40.60.81.01.21.41.61.82.02.2
Figure 15. Jitter vs. Data Rate 3.03.6
SUPPLY VOLTAGE (V)
3.13.23.33.43.5
Figure 16. Jitter vs. Supply Voltage
HDMI CABLE LENGTH (m)
ITT
(U
51015
DATA RATE (Gbps)
E H
(m
Figure 17. Jitter vs. Output Cable Length (See Figure 9 for Test Setup)
2.4
-010.20.40.60.81.01.21.41.61.82.02.2
Figure 18. Eye Height vs. Data Rate
SUPPLY VOLTAGE (V)
E H
2.62.72.82.93.03.13.23.33.43.5
Figure 19. Eye Height vs. Supply Voltage
DIFFERENTIAL INPUT SWING (V)
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless
otherwise noted.
INPUT COMMON-MODE VOLTAGE (V)
0.20.40.60.81.01.21.41.61.8
Figure 20. Jitter vs. Differential Input Swing –40100
TEMPERATURE (°C)
–20020406080
Figure 21. Jitter vs. Temperature
TEMPERATURE (°C)
20%
80%
–20020406080
Figure 22. Rise and Fall Time vs. Temperature
-022.72.93.13.33.5
Figure 23. Jitter vs. Input Common-Mode Voltage
TEMPERATURE (°C)
INAT
N RE
ANCE
–20020406080
Figure 24. Differential Input Termination Resistance vs. Temperature
THEORY OF OPERATION
INTRODUCTION
The AD8197B is a pin-to-pin HDMI 1.3 receive-compliant
replacement for the AD8197A. The primary function of the
AD8197B is to switch one of four (HDMI or DVI) single link
sources to one output. Each HDMI/DVI link consists of four
differential, high speed channels and four auxiliary single-
ended, low speed control signals. The high speed channels
include a data-word clock and three transition minimized differ-
ential signaling (TMDS) data channels running at 10× the data-
word clock frequency for data rates up to 2.25 Gbps. The four
low speed control signals are 5 V tolerant bidirectional lines
that can carry configuration signals, HDCP encryption, and
other information, depending upon the specific application.
All four high speed TMDS channels in a given link are identical;
that is, the pixel clock can be run on any of the four TMDS
channels. Transmit and receive channel compensation is
provided for the high speed channels where the user can
(manually) select among a number of fixed settings.
The AD8197B has two control interfaces. Users have the option
of controlling the part through either the parallel control
interface or the I2C serial control interface. However, the
parallel control interface is not able to control the switch status
of the input termination resistors and therefore has limited
usefulness in practical systems. Most systems use only the I2C
serial interface.
The AD8197B has eight user-programmable I2C slave addresses
to allow multiple AD8197Bs to be controlled by a single I2C bus.
A RESET pin is provided to restore the control registers of the
AD8197B to the parallel control interface and some default
values. In all cases, serial programming values override any
prior parallel programming values, and any use of the serial
control interface disables the parallel control interface until the
AD8197B is reset.
INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V
VTTI power supply through a pair of single-ended 50 Ω on-
chip resistors, as shown in Figure 25. The input termination
status for each individual high speed differential (TMDS) input
pair can be controlled by programming the appropriate RX_TO
bit in the receiver settings register. Refer to Table 5 and Table 12.
By default, the input terminations are disabled (switched open)
after reset. The input terminations cannot be switched when
programming the AD8197B through the parallel control
interface. This limits the usefulness of the parallel control
interface.
Some systems require that the input terminations be switched
on only for the one selected HDMI source. The input termina-
tions for the three unselected HDMI sources require their input
this operation, but it is not automatic. To obtain this functionality,
the channel selection and the input termination status must be
separately programmed via the I2C serial control interface.
IP_xx
IN_xx
AVEE
Figure 25. High Speed Input Simplified Schematic
The input equalizer can be manually configured to provide two
different levels of high frequency boost: 6 dB or 12 dB. The user
can individually control the equalization level of the eight high
speed input channels by selectively programming the associated
RX_EQ bits in the receive equalizer register through the serial
control interface. Alternately, the user can globally control the
equalization level of all eight high speed input channels by
setting the PP_EQ pin of the parallel control interface. No
specific cable length is suggested for a particular equalization
setting because cable performance varies widely between
manufacturers; however, in general, the equalization of the
AD8197B can be set to 12 dB without degrading the signal
integrity, even for short input cables. At the 12 dB setting, the
AD8197B can equalize more than 20 meters of 24 AWG cable at
2.25 Gbps.
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the
3.3 V VTTO power supply through two 50 Ω on-chip resistors
(see Figure 26). This termination is user-selectable; it can be
turned on or off by programming the TX_PTO bit of the
transmitter settings register through the serial control interface,
or by setting the PP_OTO pin of the parallel control interface.
The output termination resistors of the AD8197B back-
terminate the output TMDS transmission lines. These back-
terminations, as recommended in the HDMI 1.3 specification,
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the AD8197B
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
The AD8197B output has a disable feature that places the
outputs in a tristate mode. This mode is enabled by program-
ming the HS_EN bit of the high speed device modes register
through the serial control interface or by setting the PP_EN pin
of the parallel control interface. Larger wire-OR’ed arrays can be
OPxONx
AVEE
Figure 26. High Speed Output Simplified Schematic
The AD8197B requires output termination resistors when the
high speed outputs are enabled. Termination can be internal
and/or external. The internal terminations of the AD8197B are
enabled by programming the TX_PTO bit of the transmitter
settings register or by setting the PP_OTO pin of the parallel
control interface. The internal terminations of the AD8197B
default to the setting indicated by PP_OTO upon reset. External
terminations can be provided either by on-board resistors or by
the input termination resistors of an HDMI/DVI receiver. If
both the internal terminations are enabled and external termi-
nations are present, set the output current level to 20 mA by
programming the TX_OCL bit of the transmitter settings
register through the serial control interface or by setting the
PP_OCL pin of the parallel control interface. The output
current level defaults to the level indicated by PP_OCL upon
reset. If only external terminations are provided (if the internal
terminations are disabled), set the output current level to 10 mA
by programming the TX_OCL bit of the transmitter settings
register or by setting the PP_OCL pin of the parallel control
interface. The high speed outputs must be disabled if there are
no output termination resistors present in the system.
The output pre-emphasis can be manually configured to provide
one of four different levels of high frequency boost. The specific
boost level is selected by programming the TX_PE bits of the
transmitter settings register through the serial control interface,
or by setting the PP_PE bus of the parallel control interface. No
specific cable length is suggested for a particular pre-emphasis
setting because cable performance varies widely between
manufacturers.
AUXILIARY SWITCH
The auxiliary (low speed) lines have no amplification. They are
routed using a passive switch that is bandwidth compatible with
standard speed I2C. The schematic equivalent for this passive
connection is shown in Figure 27.
AUX_COM0AUX_A0
½CAUX
RAUX
Figure 27. Auxiliary Channel Simplified Schematic,
AUX_A0 to AUX_COM0 Routing Example
When turning off the AD8197B, care needs to be taken with
the AMUXVCC supply to ensure that the auxiliary multiplexer
pins remain in a high impedance state. A scenario that illustrates
this requirement is one where the auxiliary multiplexer is used
to switch the display data channel (DDC) bus. In some applica-
tions, additional devices can be connected to the DDC bus
(such as an EEPROM with EDID information) upstream of the
AD8197B.
Extended display identification data (EDID) is a VESA standard-
defined data format for conveying display configuration
information to sources to optimize display use. EDID devices
may need to be available via the DDC bus, regardless of the
state of the AD8197B and any downstream circuit. For this
configuration, the auxiliary inputs of the powered down
AD8197B need to be in a high impedance state to avoid pulling
down on the DDC lines and preventing these other devices
from using the bus.
The AD8197B requires +5 V on its supply pin, AMUXVCC, in
order for the AUXMUX channels to be high impedance. When
a TV is powered off, it cannot provide such a supply. However,
it can be provided from any HDMI source that is plugged into
it. A Schottky diode network, as shown in Figure 28, uses the
5 V supply (Pin 18) from any HDMI/DVI source to power
AMUXVCC and guarantee high impedance of the auxiliary
multiplexer pins. The AMUXVCC supply does not draw any
significant static current. The use of diodes ensures that
connected HDMI sources do not load this circuit if their +5 V
pin is low impedance when powered off. The 100 kΩ resistor
ensures that a minimum of current flows through the diodes to
keep them forward biased.
This precaution does not need to be taken if the DDC
peripheral circuitry is connected to the bus downstream of
the AD8197B. SOURCECSOURCED
PIN18HDMICONNECTORPIN14DVICONNECTOR
SOURCEA
SOURCEB
PIN18HDMIPIN14DVI
PIN18HDMICONNECTORPIN14DVICONNECTOR
+5VINTERNAL(IFANY)
BAT54LBAT54L
100kΩ
Figure 28. Suggested AMUXVCC Power Scheme

Partno	Mfg	Dc	Qty	Available	Descript
AD8197B	AD	N/a	88	avai	4:1 HDMI/DVI Switch with Equalization