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AD7750ANN/a5avaiProduct-to-Frequency Converter
AD7750ARADN/a10avaiProduct-to-Frequency Converter


AD7750AR ,Product-to-Frequency ConverterGENERAL DESCRIPTIONPRODUCT HIGHLIGHTSThe AD7750 is a Product-to-Frequency Converter (PFC)1. The par ..
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AD7750AN-AD7750AR
Product-to-Frequency Converter
REV.0
Product-to-Frequency
Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Two Differential Analog Input Channels
Product of Two Channels
Voltage-to-Frequency Conversion on a Single Channel
Real Power Measurement Capability
< 0.2% Error Over the Range 400% Ibasic to 2% Ibasic
Two or Four Quadrant Operation (Positive and
Negative Power)
Gain Select of 1 or 16 on the Current Channel (Channel 1)
Choice of On-Chip or External Reference
Choice of Output Pulse Frequencies Available
(Pins F1 and F2)
High Frequency Pulse Output for Calibration Purposes
(FOUT)
HPF on Current Channel for Offset Removal
Single 5 V Supply and Low Power
GENERAL DESCRIPTION

The AD7750 is a Product-to-Frequency Converter (PFC)
that can be configured for power measurement or voltage-to-
frequency conversion. The part contains the equivalent of two
channels of A/D conversion, a multiplier, a digital-to-frequency
converter, a reference and other conditioning circuitry. Channel 1
has a differential gain amplifier with selectable gains of 1 or 16.
Channel 2 has a differential gain amplifier with a gain of 2. A high-
pass filter can be switched into the signal path of Channel 1 to
remove any offsets.
The outputs F1 and F2 are fixed width (275 ms) logic low going
pulse streams for output frequencies less than 1.8 Hz. A range
of output frequencies is available and the frequency of F1 and
F2 is proportional to the product of V1 and V2. These outputs
are suitable for directly driving an electromechanical pulse
counter or full stepping two phase stepper motors. The outputs
can be configured to represent the result of four-quadrant multi-
plication (i.e., Sign and Magnitude) or to represent the result of
a two quadrant multiplication (i.e., Magnitude Only). In this
configuration the outputs are always positive regardless of the
input polarities. In addition, there is a reverse polarity indicator
output that becomes active when negative power is detected in
the Magnitude Only Mode, see Reverse Polarity Indicator.
The error as a percent (%) of reading is less than 0.3% over a
dynamic range of 1000:1.
The AD7750 is fabricated on 0.6 μ CMOS technology; a pro-
cess that combines low power and low cost.
PRODUCT HIGHLIGHTS
The part can be configured for power measurement or
voltage-to-frequency conversion.The output format and maximum frequency is selectable;
from low-frequency outputs, suitable for driving stepper
motors, to higher frequency outputs, suitable for calibration
and test.There is a reverse polarity indicator output that becomes
active when negative power is detected in the Magnitude
Only Mode.Error as a % of reading over a dynamic range of 1000:1 is
< 0.3%.
AD7750–SPECIFICATIONS
(VDD = 5 V 6 5%, AGND = 0V, DGND = 0 V, REFIN = +2.5V, CLKIN = 3.58 MHz
TMIN to TMAX = –408C to +858C, ACDC = Logic High)

ACCURACY
ANALOG INPUTS
REFERENCE INPUT
ON-CHIP REFERENCE
CLKIN
AD7750
ORDERING GUIDE

POWER SUPPLY
NOTESSee plots in Typical Performance Graphs.External current amplification/drive should be used if higher current source and sink capabilities are required, e.g., bipolar transistor.
All specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2

NOTESSample tested during initial release and after any redesign or process change that may affect this parameter.See Figure 18.The pulsewidths of F1, F2 and FOUT are not fixed for higher output frequencies. See the Digital-to-Frequency Converter (DTF) section for an explanation.
Specifications subject to change without notice.
(VDD = 5 V, AGND = 0V, DVDD = 0 V, REFIN = REFOUT. All specifications TMIN to TMAX
unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
Analog Input Voltage to AGND
V1+, V1–, V2+ and V2– . . . . . . . . . . . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND . . . . –0.3 V to VDD + 0.3V
Digital Input Voltage to DGND . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A Version) . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
20-Lead SOIC Package, Power Dissipation . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
20-Lead Plastic DIP, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 102°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD7750
PIN FUNCTION DESCRIPTIONS

6, 7
PIN CONFIGURATION
SOIC and DIP
VDD
REVP
FOUT
V1+
V1–
ACDC
CLKIN
CLKOUTAGND
V2+
V2–
REFOUT
REFIN
DGNDFS
Typical Performance Characteristics
50Hz RIPPLE – V rms
dBs

Figure 1.PSR as a Function of VDD 50 Hz Ripple
LINE FREQUENCY – Hz
Degrees

Figure 3.PSR as a Function of VDD 50 Hz Ripple
AD7750
V1 AMPLITUDE – mV rms
ERROR – % of Reading

Figure 4.Error as a Percentage (%) of Reading Over a
Dynamic Range of 1000, Gain = 1
V1 AMPLITUDE – mV rms
–0.5

Figure 5.Error as a Percentage (%) of Reading Over a
Dynamic Range of 1000, Gain = 16
V1 AMPLITUDE – mV rms
ERROR – % of Reading

Figure 6.Measurement Error vs. Input Signal Level and
Varying VDD with Channel 1, Gain = 1
Figure 7.Measurement Error vs. Input Signal Level and
Varying VDD with Channel 1, Gain = 16
ANALOG INPUTS
The analog inputs of the AD7750 are high impedance bipolar
voltage inputs. The four voltage inputs make up two truly
differential voltage input channels called V1 and V2. As with
any ADC, an antialiasing filter or low-pass filter is required on
the analog input. The AD7750 is designed with a unique
switched capacitor architecture that allows a bipolar analog
input with a single 5 V power supply. The four analog inputs
(V1+, V1–, V2+, V2–) each have a voltage range from –1.0 V to
+1.0 V. This is an absolute voltage range and is relative to the
ground (AGND) pin. This ground is nominally at a potential of
0 V relative to the board level ground. Figure 8 shows a very
simplified diagram of the analog input structure. When the ana-
log input voltage is sampled, the switch is closed and a very
small sampling capacitor is charged up to the input voltage. The
resistor in the diagram can be thought of as a lumped compo-
nent made up of the on resistance of various switches.
VIN
1.4kV
2pF
SAMPLING
CAPACITOR

Figure 8.Equivalent Analog Input Circuit
Analog Inputs Protection Circuitry

The analog input section also has protection circuitry. Since the
power supply rails are 0 V to 5 V, the analog inputs can no
longer be clamped to the supply rails by diodes. Thus, the inter-
nal protection circuitry monitors the current paths during a fault
condition and protects the device from continuous overvoltage,
continuous undervoltage and ESD events. The maximum over-
voltage the AD7750 analog inputs can withstand without caus-
ing irreversible damage is ±6 V relative to AGND pin.
In the case of continuous overvoltage and undervoltage the
series resistance of the antialiasing filter can be used to limit
input current. The total input current in the case of a fault
should be limited to 10 mA.
For normal operation of the AD7750 there are two further re-
strictions on the signal levels presented to the analog inputs.The voltage on any input relative to the AGND pin must not
exceed ±1 V.The differential voltage presented to the ADC (Analog
Modulator) must not exceed ±2 V.
In Figure 12, Channel 1 has a peak voltage on V1+ and V1– of
±1 V. These signals are not gained (G1 = 0) and so the
differential signal presented to the modulator is ±2 V.
However, Channel 2 has an associated gain of two and so
care must be taken to ensure the modulator input does not
exceed ±2 V. Therefore, the maximum signal voltage that
can appear on V2+ and V2– is ±0.5 V.
The difference between single-ended and complementary
differential input schemes is shown in the diagram below,
Figure 9. For a single-ended input scheme the V– input is
held at the same potential as the AGND Pin. The maxi-
mum voltages can then be applied to the V+ input are
shown in Figures 10 and 11. An example of this input
scheme uses a shunt resistor to convert the line current to a
voltage that is then applied to the V1+ input of the AD7750.
An example of the complementary differential input scheme
uses a current transformer to convert the line current to a
voltage that is then applied to V1+ and V1–. With this
scheme the voltage on the V+ input is always equal to, but
of opposite polarity to the voltage on V–. The maximum
voltage that can be applied to the inputs of the AD7750
using this scheme is shown in Figures 12 and 13.
Note that the common mode of the analog inputs must
be driven. The output terminals of the CT are, therefore,
referenced to ground.
Figure 9.Examples of Complementary and Single-
Ended Input Schemes
AD7750
V1+ = 61V MAX

61V MAX
V1– = AGND
FOUT

62V MAX
V2– = AGND
V2+ = 61V MAX

Figure 10.Maximum Input Signals with Respect to AGND for a Single-Ended Input Scheme, G1 = 0
V1+ = 6125mV MAX

62V MAX
V1– = AGND
FOUT

62V MAX2– = AGND
V2+ = 61V MAX

Figure 11.Maximum Input Signals with Respect to AGND for a Single-Ended Input Scheme, G1 = 1
V+ = 61V MAX

61V MAX
V– = 61V MAX
FOUT

61V MAX
61V MAX
61V MAX
V– = 60.5V MAX
V+ = 60.5V MAX

Figure 12.Maximum Input Signals for a Complementary Input Scheme, G1 = 0
V+ = 662.5V MAX

61V MAX
V– = 662.5V MAX
FOUT

61V MAX
61V MAX
V– = 60.5V MAX
V+ = 60.5V MAX
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