AD7660AST Fast Delivery |IC PHOENIX CO.,LIMITED

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AD7660AST
16-Bit, 100 kSPS CMOS ADC
REV.0
16-Bit, 100 kSPS CMOS ADC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Throughput: 100 kSPS
INL: �3 LSB Max (�0.0046% of Full-Scale)
16 Bits Resolution with No Missing Codes
S/(N+D): 87 dB Min, 90 dB Typ @ 10 kHz
THD: –96 dB Max @ 10 kHz
Analog Input Voltage Range: 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
Single 5 V Supply Operation
21 mW Typical Power Dissipation, 21 �W @ 100 SPS
Power-Down Mode: 7 �W Max
Package: 48-Lead Quad Flatpack (LQFP)
Pin-to-Pin Compatible with the AD7664
APPLICATIONS
Data Acquisition
Battery-Powered Systems
PCMCIA
Instrumentation
Automatic Test Equipment
Scanners
Medical Instruments
Process Control
GENERAL DESCRIPTION
The AD7660 is a 16-bit, 100 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. The part contains an internal conversion clock, error cor-
rection circuits, and both serial and parallel system interface ports.
The AD7660 is hardware factory calibrated and is comprehensively
tested to ensure such ac parameters as signal-to-noise ratio (SNR)
and total harmonic distortion (THD), in addition to the more
traditional dc parameters of gain, offset, and linearity.
It is fabricated using Analog Devices’ high-performance, 0.6
micron CMOS process with correspondingly low cost, and is
available in a 48-lead LQFP with operation specified from
–40°C to +85°C.
PRODUCT HIGHLIGHTSFast Throughput
The AD7660 is a 100 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.Superior INL
The AD7660 has a maximum integral nonlinearity of 3 LSBs
with no missing 16-bit code.Single-Supply Operation
The AD7660 operates from a single 5 V supply and only
dissipates 21mW typical. Its power dissipation decreases
with the throughput to, for instance, only 21 µW at a 100 SPS
throughput. It consumes 7 µW maximum when in power-down.Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement com-
patible with both 3 V or 5 V logic.
*Patent pending.
AD7660–SPECIFICATIONS(–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
AD7660
NOTESLSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV.Typical rms noise at worst-case transitions and temperatures.See Definition of Specifications section. These specifications do not include the error contribution from the external reference.All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.Tested in parallel reading mode.With all digital inputs forced to DVDD or DGND respectively.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Refer to Figures 18 and 20 (Slave Serial Interface Modes)
NOTESIn serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
(–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
AD7660
ABSOLUTE MAXIMUM RATINGS1
Analog Inputs2, REF . . . . . . . . . . . .AVDD + 0.3 V to AGND – 0.3 V
INGND, REFGND . . . . . . . . . . . . . . . . . . AGND ± 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . .±0.3 V
SupplyVoltages
AVDD,DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . .7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . .±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7 V
Digital Inputs
Except the Data Bus D(7:4) . . .–0.3 V to DVDD + 0.3 V
Data Bus Inputs D(7:4) . . . . . .–0.3 V to OVDD + 0.3 V
InternalPowerDissipation3 . . . . . . . . . . . . . . . . . . .700 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range
(Soldering10sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.See Analog Input section.Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θJC = 30°C/W.
Figure 1.Load Circuit for Digital Interface Timing
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7660 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
NOTESThis board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
AGND
CNVST
RESET
DGND
AGND
AVDD
DGND
OB/2C
NC = NO CONNECT
SER/PAR
BUSY
D15
D14
D13D12
D4/EXT/
INT
D5/INVSYNCD6/INVSCLK
D7/RDC/SDIN
OGND
OVDDDVDD
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERRORNCNCNCNCNCNCNCNCINGNDREFGNDREF
PIN CONFIGURATION
48-Lead LQFP
(ST-48)
Figure 2.Voltage Reference Levels for Timings
PIN FUNCTION DESCRIPTIONS
AD7660
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs 1/2LSB
before the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It is
often specified in terms of resolution for which no missing codes
are guaranteed.
FULL-SCALE ERROR
The last transition (from 011...10 to 011...11 in two’s
complement coding) should occur for an analog voltage 1 1/2 LSB
below the nominal full scale (2.49994278 V for the 0 V–2.5 V
range). The full-scale error is the deviation of the actual level of
the last transition from the ideal level.
UNIPOLAR ZERO ERROR
The first transition should occur at a level 1/2 LSB above analog
ground (19.073 µV for the 0 V–2.5 V range). Unipolar zero error is
the deviation of the actual transition from that point.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
EFFECTIVE NUMBER OF BITS (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/[N+D] by the following formula:
ENOB = (S/[N+D]dB – 1.76)/6.02
and is expressed in bits.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
SIGNAL TO (NOISE AND DISTORTION) RATIO
(S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
APERTURE DELAY
Aperture delay is a measure of the acquisition performance, and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
TRANSIENT RESPONSE
The time required for the AD7660 to achieve its rated accuracy
after a full-scale step function is applied to its input.
AD7660
–Typical Performance Characteristics
CODE
INL – LSB
327684915265536
TPC 1.Integral Nonlinearity vs. Code
TPC 2.Typical Positive INL Distribution (350 Units)
TPC 3.Histogram of 16,384 Conversions of a DC Input
at the Code Transition
CODE
DNL
LSB
–0.25
TPC 4.Differential Nonlinearity vs. Code
NEGATIVE INL – LSB
NUMBER OF UNITS
–1.2–1.8–2.4–3.0
TPC 5.Typical Negative INL Distribution (350 Units)
CODE – Hexa
COUNTS
8009800A800B800C800D800E800F8010801118800
2000
TPC 6.Histogram of 16,384 Conversions of a DC Input at
the Code Center
TPC 7.FFT Plot
TPC 8.THD, Harmonics, and SFDR vs. Frequency
TPC 9.THD, Harmonics vs. Input Level

TPC 10.SNR, S/(N+D), and ENOB vs. Frequency
TPC 11.SNR vs. Input Level
TPC 12.Typical Delay vs. Load Capacitance CL
AD7660
TPC 14.Power-Down Operating Currents vs. Temperature
TPC 13.Operating Currents vs. Sample Rate

Partno	Mfg	Dc	Qty	Available	Descript
AD7660AST	ADI	N/a	186	avai	16-Bit, 100 kSPS CMOS ADC