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AD7011ARSADN/a1172avaiCMOS, ADC p/4 DQPSK Baseband Transmit Port


AD7011ARS ,CMOS, ADC p/4 DQPSK Baseband Transmit PortSPECIFICATIONSReference, V 2.46 VoltsREFReference Accuracy ±5%I and Q Gain Matching ±0.2 dB max Mea ..
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AD7011ARS
CMOS, ADC p/4 DQPSK Baseband Transmit Port
REV.BCMOS, ADC p/4 DQPSK
Baseband Transmit Port
FEATURES
Single +5 V Supply
On-Chip p/4 DQPSK Modulator
Modulator Bypass Analog Mode
Root-Raised Cosine Tx Filters, a = 0.35
Two 10-Bit D/A Converters
4th Order Reconstruction Filters
Differential Analog Outputs
On-Chip Ramp Up/Down Power Control
On-Chip Tx Offset Calibration
Dual Mode Operation, Analog and Digital
Very Low Power Dissipation, 30 mW typical
Power Down Mode < 10
mA
On-Chip Voltage Reference
24-Pin SSOP
APPLICATIONS
American Digital Cellular Telephony
American Analog Cellular Telephony
GENERAL DESCRIPTION

The AD7011 is a complete low power, CMOS, π/4 DQPSK
modulator with single +5 V power supply. The part is designed
to perform the baseband conversion of I and Q transmit wave-
forms in accordance with the American Digital Cellular Tele-
phone system (TIA IS-54).
The on-chip π/4 Differential Quadrature Phase Shift Keying
(DQPSK) digital modulator, which includes the root raised
cosine filters, generates I and Q data in response to the transmit
data stream. The AD7011 also contains ramp control envelope
logic to shape the I and Q output waveforms when ramping up
or down at the beginning or end of a transmit burst.
Besides providing all the necessary logic to perform π/4 DQPSK
modulation, the part also provides reconstruction filters to
smooth the DAC outputs, providing continuous time analog
outputs. The AD7011 generates differential analog outputs for
both the I and Q signals.
As it is a necessity for all digital mobile systems to use the lowest
possible power, the device has transmit and receive power-down
options. The AD7011 is housed in a space efficient 24-pin
SSOP (Shrink Small Outline Package).
FUNCTIONAL BLOCK DIAGRAM
BOUT
QTxAA
MODE1
ITx
ITx
POWER
QTx
DGNDVDD
MODE2
AGND
BYPASS
BIN (Q DATA)
READY
MCLK
AD7011–SPECIFICATIONS1
(VAA = VDD = +5 V 6 10%; Test = AGND = DGND = 0 V; Digital Mode,
fMCLK = 3.1104 MHz; Analog Mode, fMCLK = 2.56 MHz, POWER = VDD. All specifications are TMIN to TMAX unless otherwise noted.)

NOTESOperating temperature ranges as follows: A Version: –40°C to +85°C.See terminology.
20k
20k
20pF
40k

Figure 1.Analog Output Test Load Circuit
MASTER CLOCK TIMING
(VAA = VDD = +5 V 6 10%; AGND = DGND = 0 V. All specifications are TMIN to TMAX unless
otherwise noted.)

Figure 3.Load Circuit for Digital Outputs
MCLK

Figure 2.Master Clock (MCLK) Timing
AD7011
TRANSMIT SECTION TIMING
MCLK
READY
BIN
TxCLK
TxDATA4571213
POWER

Figure 4.Transmit Timing at the Start of a Tx Burst
MCLK
READY
BIN
TxCLK1417
POWER
(VAA = VDD = +5 V 6 10%; AGND = DGND = 0 V, fMCLK = 3.1104 MHz. All specifications are
TMIN to TMAX unless otherwise noted.)
ANALOG MODE TIMING
(VAA = VDD = +5 V 6 10%. AGND = DGND = 0 V. All specifications are TMIN to TMAX unless
otherwise noted.)
MCLK20
FRAME
I DATA
Q DATA2324
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Figure 6.Analog Mode Serial Interface Timing
DURING FTEST

Figure 7.Modulator State During FTEST
Table I.
Table II.
AD7011
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
SSOP θJA Thermal Impedance . . . . . . . . . . . . . . . . +122°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)
VDD Tx, VDD Rx to AGND . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to AGND . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to + 150°C
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
SSOP PIN CONFIGURATION
POWER
BIN (QDATA)
TxCLK (FRAME)
TxDATA (IDATA)DD
DGND
MCLK
MODE1
BOUT
AGND
QTx
QTxAA
AGND
ITx
ITx
AGND
BYPASS
MODE2
READY
NC = NO CONNECT
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