AD7002AS ,LC2MOS GSM Baseband I/O PortSPECIFICATIONSResolution 10 Bits Rx SLEEP = V , Tx SLEEP = 0 VDDNumber of Channels 2Update Rate 4.3 ..
AD7008 ,Numerically Controlled Oscillator Employing a 32-Bit Phase Accumulator, Sine and Cosine Look-Up Tables and a 10-Bit DAC, CMOSAPPLICATIONSand asynchronously from the DDS clock; the transfer controlFrequency Synthesizerssignal ..
AD7008AP20 ,CMOS DDS Modulatorspecifications are measured using IOUT. 100% Production tested.3f = 6.25 MHz, Frequency Word = 5671 ..
AD7008JP50 ,CMOS DDS ModulatorSpecificationsSignal-to-Noise 50 50 dB f = f ,CLK MAXf = 2 MHzOUTTotal Harmonic Distortion –55 –53 ..
AD7008JP50 ,CMOS DDS ModulatorAPPLICATIONSand asynchronously from the DDS clock; the transfer controlFrequency Synthesizerssignal ..
AD7010ARS ,CMOS JDC p/4 DQPSK Baseband Transmit PortSpecifications subject to change without notice.ORDERING GUIDE Model Temperature Range Package Desc ..
ADC1173 ,8-Bit, 3-Volt, 15MSPS, 33mW A/D ConverterGeneral Description Key Specificationsn Resolution 8 BitsThe ADC1173 is a low power, 15 MSPS analog ..
ADC1173CIMTC ,8-Bit, 3-Volt, 15MSPS, 33mW A/D ConverterFeaturesn Internal Sample-and-Hold FunctionThe ADC1173 is a low power, 15 MSPS analog-to-digitalcon ..
ADC1173CIMTC ,8-Bit, 3-Volt, 15MSPS, 33mW A/D Converterapplications, including use inn Maximum Sampling Frequency 15 MSPS (min)portable equipment. Further ..
ADC1173CIMTCX ,8-Bit/ 3-Volt/ 15MSPS/ 33mW A/D ConverterPin Descriptions and Equivalent CircuitsPin Symbol Equivalent CircuitDescriptionNo.Analog signal in ..
ADC1175/50CIJM ,8-Bit, 50MSPS, 125mW A/D ConverterApplicationsmode reduces power consumption to less than 5 mW.The ADC1175-50 is offered in SOIC (EIA ..
ADC1175-50 ,8-Bit, 50 MSPS, 125 mW A/D ConverterGeneral Description
AD7002AS
LC2MOS GSM Baseband I/O Port
REV.B2MOS
GSM Baseband I/O Port
FUNCTIONAL BLOCK DIAGRAM
I Tx
Q Tx
REF OUT
I Rx
Q Rx
AUXFLAGCLK2AGND
Tx SLEEP
Tx DATA
THREE-STATE
ENABLE
Rx DATA (I DATA)
AUX DATA
AUX CLK
AUX LATCH
Rx SLEEP1
Rx SLEEP2DGNDDVDD
AUXDAC 1AUXDAC 2AUXDAC 3
CLK1MZERO
Tx CLK
Rx SYNC
Rx CLK
RATE
MODE
CAL
I/Q (Q DATA)
FEATURES
Single +5 V Supply
Transmit Channel
On-Chip GMSK Modulator
Two 10-Bit D/A Converters
Analog Reconstruction Filters
Power-Down Mode
Receive Channel
Two Sigma-Delta A/D Converters
FIR Digital Filters
On-Chip Offset Calibration
Power-Down Mode
3 Auxiliary D/A Converters
Power-Down Modes
On-Chip Voltage Reference
Low Power
44-Lead PQFP
APPLICATIONS
GSM
PCN
GENERAL DESCRIPTION
The AD7002 is a complete low power, two-channel, input/
output port with signal conditioning. The device is used as a
baseband digitization subsystem, performing signal conversion
between the DSP and the IF/RF sections in the Pan-European
telephone system (GSM).
The transmit path consists of an onboard digital modulator,
containing all the code necessary for performing Gaussian Mini-
mum Shift Keying (GMSK), two high accuracy, fast DACs with
output reconstruction filters. The receive path is composed of
two high performance sigma-delta ADCs with digital filtering. A
common bandgap reference feeds the ADCs and signal DACs.
Three control DACs (AUX DAC1 to AUX DAC3) are in-
cluded for such functions as AFC, AGC and carrier signal shap-
ing. In addition, AUX FLAG may be used for routing digital
control information through the device to the IF/RF sections.
As it is a necessity for all GSM mobile systems to use the lowest
power possible, the device has power-down or sleep options for
all sections (transmit, receive and auxiliary).
The AD7002 is housed in 44-lead PQFP (Plastic Quad Flatpack).
AD7002–SPECIFICATIONS1
TRANSMIT DAC SPECIFICATIONS
(AVDD = +5 V 6 10%; DVDD = +5 V 6 10%; AGND = DGND = 0 V, fCLK1 = fCLK2 = 13 MHz;
TA = TMIN to TMAX, Rx SLEEP1 = Rx SLEEP2 = Tx SLEEP = DVDD, unless otherwise noted)
AD7002
REFERENCE SPECIFICATIONS
LOGIC INPUTS
LOGIC OUTPUTS
POWER SUPPLIES
NOTESOperating temperature range: A Version: –40°C to +85°C.Unmeasurable: sigma-delta conversion is inherently free of differential nonlinearities.See terminology.Change in reference voltage due to a change in Tx SLEEP or Rx SLEEP modes.Measured while the digital inputs to the transmit interface are static.Measured while the digital inputs to the receive interface are static.Measured while the digital inputs to the auxiliary interface are static.
Specifications subject to change without notice.
AD7002
TERMINOLOGY
Absolute Group Delay
Absolute group delay is the rate of change of phase versus fre-
quency, dθ/df. It is expressed in microseconds.
Bias Offset Error
This is the offset error (in LSBs) in the ADC section.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the DAC
or ADC.
Dynamic Range
Dynamic Range is the ratio of the maximum output signal to the
smallest output signal the converter can produce (1 LSB), ex-
pressed logarithmically, in decibels (dB = 20log10 (ratio)). For
an N-bit converter, the ratio is theoretically very nearly equal toN (in dB, 20Nlog10(2) = 6.02N). However, this theoretical
value is degraded by converter noise and inaccuracies in the
LSB weight.
Full-Scale Accuracy
This is the measure of the ADC full-scale error after the offset
has been adjusted out.
Gain Error
This is a measure of the output error between an ideal DAC and
the actual device output with all ls loaded after offset error has
been adjusted out and is expressed in LSBs. In the AD7002,
gain error is specified for the auxiliary section.
Gain Matching Between Channels
This is the gain matching between the ITx and QTx channel
and is expressed in dBs.
GMSK Spectrum Mask
This is the combined output spectrum of the I and Q analog
outputs when transmitting a random sequence of data bits on
the AD7002 transmit channel.
AMPLITUDE –
dB
FREQUENCY – kHz
AD7002 Transmit GMSK Spectrum Mask
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . . .–0.3 V to DVDD + 0.3 V
Analog Input Voltage to AGND . . . .–0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . .±10 mA
Operating Temperature Range
Industrial Plastic (A Version) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . .450 mW
Derates Above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at those or any other conditions above those listed in the operational sections
of this specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
PIN DESCRIPTION
AUX FLAG
AUX LATCH
AUX CLK
AUX DATA
MZERO
Rx SLEEP1
TEST2
Rx SLEEP2
CAL
Tx SLEEP
Tx DATA
CLK2
Tx CLK
DGND
CLK1
TEST115161718192021434241403937
I RxTEST4Q RxI TxREFOUTQ TxAGNDAVAUX DAC2AUX DAC3AUX DAC1
RATE
MODE
TEST3
DGND
Rx DATA (IDATA)
Rx SYNC
Rx CLK
3-STATE ENABLE
NC = NO CONNECT
I/Q (QDATA)
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
GMSK Phase Trajectory Error
This is a measure of the phase error between the transmitted
phase of an ideal GMSK modulator and the actual phase trans-
mitted by the AD7002, when transmitting a random sequence
of data bits. It is specified as a peak phase error and also as an
rms phase error.
Group Delay Linearity
The group delay linearity, or differential group delay, is the
group delay over the full band relative to the group delay at one
particular frequency. The reference frequency for the AD7002 is
1 kHz.
Group Delay Between Channels
This is the difference between the group delay of the I and Q
channels and is a measure of the phase matching characteristics
of the two.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the DAC or ADC transfer function.
Maximum Phase Effect Instance
This is the time at which a transmitted data bit will have its
maximum phase change at the ITx and QTx outputs (see fig-
ure). This time includes the delay in the GMSK modulator and
in the Analog low-pass filters. Maximum phase effect instance is
measured from the Tx CLK falling edge, which latches the data
bit, to the ITx and QTx analog outputs.
90°
DATA BIT
CLOCKED IN BY TxCLK
MAXIMUM PHASE
EFFECT INSTANT
TRANSMITTED PHASE
FOR ONE DATA BIT
45°
Transmit Channel Maximum Phase Effect Instance
Output Rate
This is the rate at which data words are made available at the
Rx DATA pin (Mode 0) or the IDATA and QDATA pins
(Mode 1). There are two rates, depending on whether the de-
vice is operated in RATE0 or RATE1.
Offset Error
This is the amount of offset, w.r.t. VREF in the transmit DACs
and the auxiliary DACs and is expressed in mVs for the Trans-
mit section and in LSBs for the Auxiliary section.
Output Impedance
This is a measure of the drive capability of the auxiliary DAC
outputs and is expressed in kΩs.
Output Signal Span
This is the output signal range for the Transmit Channel section
and the Auxiliary DAC section. For the transmit channel the
span is ±1.25 volts centered on 2.5 volts, and for the Auxiliary
DAC section it is 0 to +VREF.
Output Signal Full-Scale Accuracy
This is the accuracy of the full-scale output (all 1s loaded to the
DACs) on each transmit channel measured w.r.t. 25 V and is
expressed in dBs.
Phase Matching Between Channels
This is a measure of the phase matching characteristics of the I
and Q transmit channels. It is obtained by transmitting all ones
and then measuring the difference between the actual phase
shift between the I and Q outputs and the ideal phase shift of
90°.
Sampling Rate
This is the rate at which the modulators on the receive channels
sample the analog input.
Settling Time
This is the digital filter settling time in the AD7002 receive
section. On initial power-up, or after returning from the sleep
mode, it is necessary to wait this amount of time to obtain use-
ful data.
Signal Input Span
The input signal range for the I and Q channels is biased about
VREF. It can go ±1.25 volts about this point.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at the
output of the receive channel. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all amplitude of the
fundamental. Noise is the rms sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent upon the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal-to-(noise+distortion) ratio for
a sine wave is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
AD7002
INPUT CLOCK TIMING1
TRANSMIT SECTION TIMING
t10
t14
AUXILIARY DAC TIMING
t16
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.t13 specifies a window, that Tx SLEEP should be asserted for the current Tx CLK to be the last prior to entering SLEEP mode.Digital output rise and fall times specify the time required for the output to go between 10% and 90% of 5 V.
Specifications subject to change without notice.
(AVDD = +5 V 6 10%; DVDD = +5 V 6 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted)
(AVDD = +5 V 6 10%; DVDD = +5 V 6 10%; AGND = DGND = 0 V, fCLK1 = fCLK2 = 13 MHz;
TA = TMIN to TMAX, unless otherwise noted)
CLK1, CLK2,
AUX CLK
TO OUTPUT
PIN+2.1V
IOL1.6mA
IOH200mA
CL
15pF
(AVDD = +5 V 6 10%; DVDD = +5 V 6 10%; AGND = DGND = 0 V, fAUX CLK = 13 MHz; TA = TMIN to TMAX,
unless otherwise noted)
RECEIVE SECTION TIMING1
t23
t26
t27
t28
t33
t34
t36
CALIBRATION AND CONTROL TIMING
t38
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.t25 specifies a window, after Rx SYNC which marks the beginning of I data, that Rx SLEEP should be asserted for the subsequent IQ data pair to be last prior to
entering SLEEP mode.See Figure 2 for test circuit.Digital output rise and fall times specify the time required for the output to go between 10% and 90% of 5 V.
Specifications subject to change without notice.
(AVDD = +5 V 6 10%; DVDD = +5 V 6 10%; AGND = DGND = 0 V, fCLK1 = fCLK2 = 13 MHz;
TA = TMIN to TMAX, unless otherwise noted)
(AVDD = +5 V 6 10%; DVDD = +5 V 6 10%; AGND = DGND = 0 V, fAUX CLK = 13 MHz;
TA = TMIN to TMAX, unless otherwise noted)
AD7002
CIRCUIT DESCRIPTION
TRANSMIT SECTION
The transmit section of the AD7002 generates GMSK I and Q
waveforms in accordance with GSM recommendation 5.04.
This is accomplished by a digital GMSK modulator, followed
by 10-bit DACs for the I and Q channels and on-chip recon-
struction filters. The GMSK (Gaussian Minimum Shift Keying)
digital modulator generates I and Q signals, at 163 oversam-
pling, in response to the transmit data stream. The I and Q data
streams drive 10-bit DACs, which are filtered by on-chip Bessel
low-pass filters.
IDATA
QDATATx DATA
Figure 3.GMSK Functional Block Diagram
Table I.Truth Table for the Differential Encoder
GMSK Modulator
Figure 3 shows the functional block diagram of the GMSK
modulator. This is implemented using control logic with a
ROM look up table, to generate I and Q data samples at
16 times the transmit data rate. The transmit data (Tx DATA)
is first differentially encoded as specified by GSM 5.04 section
2.3 (Table I). The GMSK modulator generates 10-bit I and Q
waveforms (Inphase and Quadrature), in response to the en-
coded data, which are loaded into the 10-bit I and Q transmit
DACs. The Gaussian filter, in the GMSK modulator, has an
impulse response truncated to four data bits.
When the transmit section is brought out of sleep mode
(Tx SLEEP low), the modulator is reset to a transmitting all 1s
state. When Tx SLEEP is asserted (Tx SLEEP high), the trans-
mit section powers down, with the I Tx and Q Tx outputs con-
nected to VREF through a nominal impedance of 80 kΩ.
Reconstruction Filters
The reconstruction filters smooth the DAC output signals,
providing continuous time I and Q waveforms at the output
pins. These are Bessel low-pass filters with a cutoff frequency of
approximately 300 kHz. Figure 5 shows a typical transmit filter
frequency response, while Figure 6 shows a typical plot of group
delay versus frequency. The filters are designed to have a linear
phase response in the passband and due to the reconstruction
filters being on-chip, the phase mismatch between the I and Q
transmit channels is kept to a minimum.
Transmit Section Digital Interface
Figure 4 shows the timing diagram for the transmit interface.
Tx SLEEP is sampled on the falling edge of CLK1. When
Tx SLEEP is brought low, Tx CLK becomes active after 24
master clock cycles. Tx CLK can be used to clock out the
transmit data from the ASIC or DSP on the rising edge and
Tx DATA is clocked into the AD7002 on the falling edge of
Tx CLK. When Tx SLEEP is asserted the transmit section is
immediately put into sleep mode, disabling Tx CLK and power-
ing down the transmit section.
CLK1 (I)
Tx SLEEP (I)
Tx CLK (O)
Tx DATA (I)
NOTE: (I) = DIGITAL INPUT; (0) = DIGITAL OUTPUT
Figure 4.Transmit Section Timing Diagram
