AD679KD ,14-Bit 128 kSPS Complete Sampling ADCSPECIFICATIONSMIN MAX CC EE DDAD679J/A/S AD679K/B/TParameter Min Typ Max Min Typ Max UnitsTEMPERATU ..
AD680 ,Bandgap, Low Power 2.5v Referenceapplications such as5. Plastic DIP packaging provides machine insertability, whilehand-held battery ..
AD680AN ,Low Power, Low Cost 2.5 V ReferenceSPECIFICATIONS (T = +258C, V = +5 V, unless otherwise noted)A IN AD680AN/AR AD680JN/JR ..
AD680AR ,Low Power, Low Cost 2.5 V ReferenceFEATURESLow Quiescent Current: 250 mA maxLaser Trimmed to High Accuracy:TP* 1 8 TP*2.5 V 65 mV max ..
AD680JN ,Low Power, Low Cost 2.5 V ReferenceLow Power, Low Costa2.5 V ReferenceAD680*CONNECTION DIAGRAMS
AD680JN. ,Low Power, Low Cost 2.5 V ReferenceSpecifications in boldface are tested on all production units at final eleetrical test. Results fro ..
ADC1001CCJ ,10-Bit µP Compatible A/D Converter [Life-time buy]electrical specifications do not apply when operatingthe device beyond its specified operating cond ..
ADC1001CCJ-1 ,10-Bit µP Compatible A/D Converter [Life-time buy]Featuresn ADC1001 is pin compatible with ADC0801 series 8-bitThe ADC1001 is a CMOS, 10-bit successi ..
ADC10030CIVT ,10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and HoldGeneral Descriptionn Guaranteed No Missing CodesThe ADC10030 is a low power, high performance CMOSn ..
ADC10030CIVTX ,10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Holdapplications, and itsn Document Scannersspeed and resolution are ideal for charge coupled devicen M ..
ADC10040CIMT ,10-Bit, 40 MSPS, 3V, 55.5 mW A/D ConverterFeaturesn Single +3.0V operationTheADC10040 is a monolithic CMOS analog-to-digital con-verter capab ..
ADC10040CIMT/NOPB ,10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter 28-TSSOP -40 to 85FEATURES DESCRIPTIONThe ADC10040 is a monolithic CMOS analog-to-2• Single +3.0V Operationdigital co ..
AD679JD-AD679KD
14-Bit 128 kSPS Complete Sampling ADC
FUNCTIONAL BLOCK DIAGRAMREV.C
14-Bit 128 kSPS
Complete Sampling ADC
FEATURES
AC and DC Characterized and Specified
(K, B, T Grades)
128k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
80 dB S/N+D (K, B, T Grades)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 MV Input Impedance
8-Bit Bus Interface (See AD779 for 16-Bit Interface)
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
Pin Compatible with AD678 12-Bit, 200 kSPS ADC
MIL-STD-883 Compliant Versions Available
PRODUCT HIGHLIGHTSCOMPLETE INTEGRATION: The AD679 minimizes
external component requirements by combining a high
speed sample-hold amplifier (SHA), ADC, 5 V reference,
clock and digital interface on a single chip. This provides a
fully specified sampling A/D function unattainable with
discrete designs.SPECIFICATIONS: The AD679K, B and T grades provide
fully specified and tested ac and dc parameters. The AD679J,
A and S grades are specified and tested for ac parameters; dc
accuracy specifications are shown as typicals. DC specifica-
tions (such as INL, gain and offset) are important in control
and measurement applications. AC specifications (such as
S/N+D ratio, THD and IMD) are of value in signal process-
ing applications.EASE OF USE: The pinout is designed for easy board lay-
out, and the two read output provides compatibility with 8-
bit buses. Factory trimming eliminates the need for calibration
modes or external trimming to achieve rated performance.RELIABILITY: The AD679 utilizes Analog Devices’ mono-
lithic BiMOS technology. This ensures long term reliability
compared to multichip and hybrid designs.UPGRADE PATH: The AD679 provides the same pinout as
the 12-bit, 200 kSPS AD678 ADC.The AD679 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD679/883B data sheet for detailed
specifications.
GENERAL DESCRIPTIONThe AD679 is a complete, multipurpose 14-bit monolithic
analog-to-digital converter, consisting of a sample-hold ampli-
fier (SHA), a microprocessor compatible bus interface, a voltage
reference and clock generation circuitry.
The AD679 is specified for ac (or “dynamic”) parameters such
as S/N+D ratio, THD and IMD which are important in signal
processing applications. In addition, the AD679K, B and T
grades are fully specified for dc parameters which are important
in measurement applications.
The 14 data bits are accessed in two read operations (8+6), with
left justification. Data format is straight binary for unipolar
mode and twos complement binary for bipolar mode. The input
has a full-scale range of 10 V with a full power bandwidth of
1 MHz and a full linear bandwidth of 500 kHz. High input im-
pedance (10 MΩ) allows direct connection to unbuffered
sources without signal degradation. Conversions can be initiated
either under microprocessor control or by an external clock
asynchronous to the system clock.
This product is fabricated on Analog Devices’ BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging al-
gorithm which includes error correction and flash converter cir-
cuitry to achieve high speed and resolution.
The AD679 operates from +5 V and ±12 V supplies and dissi-
pates 560 mW (typ). 28-pin plastic DIP, ceramic DIP and 44
J-leaded ceramic surface mount packages are available.
*. Patent Nos. 4,804,960; 4,814,767; 4,833,345; 4,250,445;
4,808,908; RE 30,586
AD679–SPECIFICATIONS
AC SPECIFICATIONSTOTAL HARMONIC DISTORTION (THD)
DIGITAL SPECIFICATIONSNOTESflN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal
unless otherwise noted.See Figure 15 for higher frequencies and other input amplitudes.See Figures 13 and 14 for higher frequencies and other input amplitudes.fA = 9.08 kHz, fB = 9.58 kHz, with fSAMPLE 100 kSPS. See Definition of Specifications section.
Specifications subject to change without notice.
(All device types TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)
(TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%, fSAMPLE = 128 kSPS, fIN = 10.009 kHz
unless otherwise noted)1
DC SPECIFICATIONSACCURACY
ANALOG INPUT
POWER SUPPLIES
NOTESAdjustable to zero. See Figures 5 and 6.Includes internal voltage reference error.Includes internal voltage reference drift.Excludes internal voltage reference drift.
(TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10% unless otherwise noted)
AD679
AD679
TIMING SPECIFICATIONS
(All device types TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%,
VDD = +5 V 6 10%)NOTESIncludes Acquisition Time.Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the
data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.COUT = 100 pF.COUT = 50 pF.Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the
output voltage changes by 0.5. See Figure 4; COUT = 10 pF.
Specifications subject to change without notice.
ORDERING GUIDE1NOTESFor parallel read (14-bits) interface to 16-bit buses, see AD779.For details grade and package offerings screened in accordance with MIL-STD-
883, refer to the Analog Devices Miliary Products Databook or current AD679/
883B data sheet.N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier.
Figure 1. Conversion Timing
Figure 2.Output Timing
Figure 3.EOC Timing
ABSOLUTE MAXIMUM RATINGS*
CAUTIONThe AD679 features input protection circuitry consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast,
low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD679 has
been classified as a Category 1 device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test equip-
ment and discharge without detection. Unused devices must be stored in conductive foam or shunts,
and the foam should be discharged to the destination socket before devices are removed. For further
information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.
NOTES
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.The AD679 is not designed to operate from ±15 V supplies.
OUTLINE DIMENSIONSDimensions shown in inches and (mm).
44-Lead J-Leaded Chip Carrier (J-44)28-Pin Ceramic DIP Package (D-28)
28-Lead Plastic DIP Package (N-28)
AD679
PIN DESCRIPTIONDGND
DB7–DB0
EOC
REFOUT
SYNC
VEE
VDD
Type: AI = Analog Input. AO = Analog Output. DI = Digital Input (TTL and 5 V CMOS compatible). DO = Digital Output (TTL and 5 V CMOS compatible).
All DO pins are three-state drivers. P = Power. U = Unused.
PIN CONFIGURATIONDIP PackageJLCC Package
