AD674BAR ,0-16.5V; 825mW; complete 12-bit A/D ConverterFEATURES FUNCTIONAL BLOCK DIAGRAMComplete Monolithic 12-Bit A/D Converters withReference, Clock, an ..
AD674BBD ,Complete 12-Bit A/D ConvertersFEATURESComplete Monolithic 12-Bit A/D Converters withReference, Clock, and Three-State Output Buff ..
AD674BBR ,0-16.5V; 825mW; complete 12-bit A/D ConverterSPECIFICATIONS to T with V = +15 V 10% or +12 V 5%,MIN MAX CCV = +5 V 10%, V = –15 V 10% or ..
AD674BJN ,Complete 12-Bit A/D Convertersspecifications.grades are available in a 28-pin hermetically sealed ceramicDIP.*Protected by U.S. P ..
AD674BKN ,Complete 12-Bit A/D ConvertersSpecifications shown in boldface are tested on all devices at final electrical test at T , +25°C, a ..
AD674BTD ,Complete 12-Bit A/D Convertersspecifications.grades are available in a 28-pin hermetically sealed ceramicDIP.*Protected by U.S. P ..
ADC0844CCN .. ,8-Bit Microprocessor Compatible A/D Converter with Multiplexer OptionADC0844/ADC0848 8-Bit μP Compatible A/D Converters with Multiplexer OptionsJune 1999ADC0844/ADC0848 ..
ADC0848BCN ,8-Bit Microprocessor Compatible A/D Converter with Multiplexer OptionFeaturesn Easy interface to all microprocessorsThe ADC0844 and ADC0848 are CMOS 8-bit successiveapp ..
ADC0848BCV ,8-Bit Microprocessor Compatible A/D Converter with Multiplexer OptionFeaturesn Easy interface to all microprocessorsThe ADC0844 and ADC0848 are CMOS 8-bit successiveapp ..
ADC0848CCJ ,8-Bit Microprocessor Compatible A/D Converter with Multiplexer OptionFeaturesn Easy interface to all microprocessorsThe ADC0844 and ADC0848 are CMOS 8-bit successiveapp ..
ADC0848CCJ ,8-Bit Microprocessor Compatible A/D Converter with Multiplexer OptionADC0844/ADC0848 8-Bit μP Compatible A/D Converters with Multiplexer OptionsJune 1999ADC0844/ADC0848 ..
ADC0848CCN ,8-Bit Microprocessor Compatible A/D Converter with Multiplexer OptionFeaturesn Easy interface to all microprocessorsThe ADC0844 and ADC0848 are CMOS 8-bit successiveapp ..
AD674BAR-AD674BBR
0-16.5V; 825mW; complete 12-bit A/D Converter
FUNCTIONAL BLOCK DIAGRAMREV.C
Complete 12-Bit
A/D Converters
FEATURES
Complete Monolithic 12-Bit A/D Converters with
Reference, Clock, and Three-State Output Buffers
Industry Standard Pinout
High Speed Upgrades for AD574A
8- and 16-Bit Microprocessor Interface
8 �s (Max) Conversion Time (AD774B)
15 �s (Max) Conversion Time (AD674B)�5 V, �10 V, 0 V–10 V, 0 V–20 V Input Ranges
Commercial, Industrial, and Military Temperature
Range Grades
MIL-STD-883-Compliant Versions Available
PRODUCT DESCRIPTIONThe AD674B and AD774B are complete 12-bit successive-
approximation analog-to-digital converters with three-state
output buffer circuitry for direct interface to 8- and 16-bit
microprocessor busses. A high-precision voltage reference and
clock are included on chip, and the circuit requires only power
supplies and control signals for operation.
The AD674B and AD774B are pin-compatible with the indus-
try standard AD574A, but offer faster conversion time and bus-
access speed than the AD574A and lower power consumption.
The AD674B converts in 15 µs (maximum) and the AD774B
converts in 8 µs (maximum).
The monolithic design is implemented using Analog Devices’
BiMOS II process allowing high-performance bipolar analog
circuitry to be combined on the same die with digital CMOS logic.
Offset, linearity, and scaling errors are minimized by active
laser trimming of thin-film resistors.
Five different grades are available. The J and K grades are
specified for operation over the 0°C to 70°C temperature range.
The A and B grades are specified from –40°C to +85°C, the T grade
is specified from –55°C to +125°C. The J and K grades are
available in a 28-lead plastic DIP or 28-lead SOIC. All other grades
are available in a 28-lead hermetically sealed ceramic DIP.
PRODUCT HIGHLIGHTSIndustry Standard Pinout: The AD674B and AD774B use
the pinout established by the industry standard AD574A.Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges: 0 V to
10 V and 0 V to 20 V unipolar; –5 V to +5 V and –10 V to
+10 V bipolar. The AD674B and AD774B operate on +5 V
and ±12 V or ±15 V power supplies.Flexible Digital Interface: On-chip multiple-mode three-state
output buffers and interface logic allow direct connection to
most microprocessors. The 12 bits of output data can be
read either as one 12-bit word or as two 8-bit bytes (one with
8 data bits, the other with 4 data bits and 4 trailing zeros).The internal reference is trimmed to 10.00 V with 1% maxi-
mum error and 10 ppm/°C typical temperature coefficient.
The reference is available externally and can drive up to
2.0 mA beyond the requirements of the converter and bipo-
lar offset resistors.The AD674B and AD774B are available in versions compli-
ant with MIL-STD-883. Refer to the Analog Devices Mili-
tary Products Databook or current AD674B/AD774B/883B
data sheet for detailed specifications.
*. Patent Nos. 4,250,445; 4,808,908; RE30586.
DIFFERENTIAL LINEARITY ERROR
FULL-SCALE CALIBRATION ERROR
POWER SUPPLY REJECTION
ANALOG INPUT
NOTES
1Adjustable to zero.
2Includes internal voltage reference error.
3Maximum change from 25°C value to the value at TMIN or TMAX.
4Tested with REF OUT tied to REF IN through 50 Ω resistor, VCC = +16.5 V, VEE = –16.5 V, VLOGIC = +5.5 V, and outputs in high-Z mode.
5Tested with REF OUT tied to REF IN through 50 Ω resistor, VCC = +12 V, VEE = –12 V, VLOGIC = +5 V, and outputs in high-Z mode.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at TMIN, 25°C, and TMAX. Results from those tests are used to calculate outgoing quality levels. All min and
AD674B/AD774B–SPECIFICATIONS (TMIN to TMAX with VCC = +15 V � 10% or +12 V � 5%,
VLOGIC = +5 V � 10%, VEE = –15 V � 10% or –12 V � 5%, unless otherwise noted.)
CONVERTER START TIMING (Figure 1)
READ TIMING—FULL CONTROL MODE (Figure 2)Output Float Delay
NOTEStDD is measured with the load circuit of Figure 3a and is defined as the time required
for an output to cross 0.4 V or 2.4 V.0°C to TMAX.At –40°C.At –55°C.tHL is defined as the time required for the data lines to change 0.5 V when loaded with
the circuit of Figure 3b.
Specifications shown in boldface are tested on all devices at final electrical test with
IIH
LOGIC OUTPUTS
VOH
VOL
DIGITAL SPECIFICATIONS
(For all grades TMIN to TMAX with VCC = +15 V � 10% or +12 V � 5%, VLOGIC = +5 V � 10%,
VEE = –15 V � 10% or –12 V � 5%, unless otherwise noted.)
SWITCHING SPECIFICATIONS
(For all grades TMIN to TMAX with VCC = +15 V � 10% or +12 V � 5%,
VLOGIC = +5 V � 10%, VEE = –15 V � 10% or –12 V � 5%, unless otherwise noted.)Figure 1. Convert Start Timing
Figure 2. Read Cycle Timing
DBN
3k�100pF
DBN
3k�
100pF
HIGH-Z TO LOGIC 0HIGH-Z TO LOGIC 1 High-Z to Logic 1 High-Z to Logic 0
Figure 3a. Load Circuit for Access Time Test
DBN
3k�100pF
DBN
3k�
100pF
AD674B/AD774B
AD674B/AD774B
TIMING—STAND ALONE MODE (Figures 4a and 4b)Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*VCC to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +16.5 V
VEE to Digital Common . . . . . . . . . . . . . . . . . . . . 0 to –16.5 V
VLOGIC to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +7 V
Analog Common to Digital Common . . . . . . . . . . . . . . . ±1 V
Digital Inputs to Digital Common . . . –0.5 V to VLOGIC +0.5 V
Analog Inputs to Analog Common . . . . . . . . . . . . VEE to VCC
20 VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . ±24 V
REF OUT . . . . . . . . . . . . . . . . . .Indefinite Short to Common
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .Momentary Short to VCC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .175°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . .300°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Flgure 4a. Standalone Mode Timing Low Pulse R/C
Figure 4b. Standalone Mode Timing High Pulse for R/C
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ORDERING GUIDENOTESFor details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military
Products Databook or the current AD674B/ AD774B/883B data sheet.N = Plastic DIP; D = Hermetic DIP; R = Plastic SOIC.
DEFINITION OF SPECIFICATIONS
Linearity ErrorLinearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale.” The point
used as “zero” occurs 1/2 LSB (1.22 mV for 10 V span) before
the first code transition (all zeroes to only the LSB “on”). “Full
scale” is defined as a level 1 1/2 LSB beyond the last code tran-
sition (to all ones). The deviation of a code from the true straight
line is measured from the middle of each particular code.
The K, B, and T grades are guaranteed for maximum nonlinear-
ity of ±1/2 LSB. For these grades, this means that an analog
value that falls exactly in the center of a given code width will
result in the correct digital output code. Values nearer the upper
or lower transition of the code width may produce the next upper
or lower digital output code. The J and A grades are guaranteed
to ±1 LSB max error. For these grades, an analog value that
falls within a given code width will result in either the correct
code for that region or either adjacent one.
Note that the linearity error is not user adjustable.
Differential Linearity Error (No Missing Codes)A specification that guarantees no missing codes requires that
every code combination appear in a monotonic increasing sequence
as the analog input level is increased. Thus every code must have a
finite width. The AD674B and AD774B guarantee no missing codes
to 12-bit resolution, requiring that all 4096 codes must be present
over the entire operating temperature ranges.
Unipolar OffsetThe first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the actual
transition from that point. This offset can be adjusted as discussed
later. The unipolar offset temperature coefficient specifies the
maximum change of the transition point over temperature,
with or without external adjustment.
Bipolar OffsetIn the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
Quantization UncertaintyAnalog-to-digital converters exhibit an inherent quantization
uncertainty of ±1/2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be reduced
for a converter of given resolution.
Left-Justified DataThe output data format is left-justified. This means that the
data represents the analog input as a fraction of full scale, rang-
ing from 0 to 4095/4096. This implies a binary point 4095 to
the left of the MSB.
Full-Scale Calibration ErrorThe last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 V for 10.000 V full scale). The full-scale cali-
bration error is the deviation of the actual level at the last transi-
tion from the ideal level. This error, which is typically 0.05% to
0.1% of full scale, can be trimmed out as shown in Figures 7
and 8. The full-scale calibration error over temperature is given
with and without the initial error trimmed out. The temperature
coefficients for each grade indicate the maximum change in the
full-scale gain from the initial value using the internal 10 V
reference.
Temperature DriftThe temperature drift for full-scale calibration, unipolar offset,
and bipolar offset specifies the maximum change from the initial
(25°C) value to the value at TMIN or TMAX.
Power Supply RejectionThe standard specifications assume use of +5.00 V and ±15.00 V
or ±12.00 V supplies. The only effect of power supply error on
the performance of the device will be a small change in the
full-scale calibration. This will result in a linear change in all
low-order codes. The specifications show the maximum full-
scale change from the initial value with the supplies at the
various limits.
Code WidthA fundamental quantity for A/D converter specifications is the
code width. This is defined as the range of analog input values for
which a given digital output code will occur. The nominal value
of a code width is equivalent to 1 least significant bit (LSB) of the
full-scale range or 2.44 mV out of 10 V for a 12-bit ADC.
AD674B/AD774B
PIN FUNCTION DESCRIPTIONSDB11–DB8
REF IN
STS
VCC
VEE
10 VIN
PIN CONFIGURATION
