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AD6411AST
DECT RF Transceiver
REV.0
DECT RF Transceiver
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fully Compliant with DECT Specifications
Single IC DECT Radio
Integrated UHF VCO (External Resonator)
Integrated Synthesizer Supporting Extended Frequency
Allocation
Built-In Supply Regulation
Direct VCO Modulation for DECT Transmit Path
PLL-Based Demodulator
Use with Low Cost Plastic Packaged SAW Filters
Ultralow Power Design
Operates from +3.0 V to +5.5 V Battery
User-Selectable Power-Down Modes
Small 48-Lead LQFP Package
APPLICATIONS
DECT Cordless Telephones
DECT-Based Wireless Local Loop Systems
DECT-Based Wireless Data Systems
DESCRIPTIONThe AD6411 provides the complete transmit and receive RF
signal processing necessary to implement a digital wireless
transceiver based on the Digital Enhanced Cordless Telecom-
munications (DECT) standard.
The AD6411’s receive signal path consists of a mixer, IF ampli-
fiers and PLL demodulator. The low noise, high intercept mixer
is a development of the doubly-balanced Gilbert-Cell type. It
has a nominal –16 dBm input-referred 1 dB compression point
and a –8 dBm input referred third-order intercept. The limiter
amplifier provides sufficient gain to drive the PLL demodulator,
which provides selectable analog or sliced outputs. The RSSI
output provides a voltage proportional to the receive signal
strength. It measures nearly 100 dB IF signal strength range
with 14 mV/dB gain scaling.
The transmit path accepts baseband data, which is filtered and
applied to the VCO directly. The VCO operates at half the RF
carrier frequency, and is doubled to avoid pulling due to leakage
from the output.
An on-chip PLL frequency synthesizer provides channel selec-
tion. Operating modes are selected either through a serial bus or
asynchronous control pins. This allows compatibility with most
of the available DECT baseband controller ASICs.
The AD6411 is packaged in a 48-lead LQFP.
AD6411–SPECIFICATIONS(TA = 258C, 3.0 V < VBAT < 5.5 V unless otherwise noted)
AD6411POWER CONSUMPTION
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5.5 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . .600 mW
Operating Temperature Range . . . . . . . . . . .–25°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature, Soldering 60 sec . . . . . . . . . . . . . .+300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended rating conditions for extended periods may affect device
reliability.Thermal Characteristics: 48-lead LQFP package: qJA = +126°C/W.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6411 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
48-Lead LQFP (ST-48)
BSWDATA
VF2VCCPDVCOB
VCCVCO
VCOGNDVBAT1
GND
VCCTX
GND
GND
TXOP
GND
GND
RSSI
VCCIF2
GND
IFINB
IFIN
VCCIF1
REF
SFS
DEMODENAB
COFF
DMR
IFLF
IFCP
IFVCO
VREF
GND
GND
RFIN
GND
VCCRX
VS1
VF1
SYN
VBAT2
CLK
MXOP
VCCDMGND
AD6411
PIN FUNCTION DESCRIPTIONS
PRODUCT OVERVIEWThe AD6411 provides most of the active circuitry required to
realize a complete low power DECT transceiver.
Figure 1 shows the main sections of the AD6411. It consists, in
the receive path, of a UHF mixer and two-stage IF strip with
integrated demodulator and data slicer. The transmit path con-
sists of a VCO, frequency doubler and buffer amplifier.
Channel selection is performed by an on-chip PLL synthesizer.
All AD6411 operating modes can be controlled by parallel con-
trol inputs or the serial interface.
Receive MixerThe UHF mixer is an improved Gilbert-cell design. The dy-
namic range at the input of the mixer is determined, at the up-
per end, by the maximum input signal level of –16 dBm in 50 W
at RFIN up to which the mixer remains linear and a valid RSSI
signal is provided and, at the lower end, by the noise level.
The local oscillator input of the receive mixer is internally pro-
vided by the LO, which is obtained by doubling the on-chip
VCO frequency.
The output of the mixer is single-ended. The nominal conver-
sion gain is specified for operation into a 110.592 MHz or
112.32 MHz SAW IF DECT bandpass filter. The power gain
of 17 dB is measured between the mixer input and the input of
this filter.
IF Circuits and DemodulatorDemodulation is achieved via a PLL. This is shown in detail in
Figure 2. An external manufacturing trim is required to achieve
the required level of frequency accuracy. The approach is to
adjust the capacitor TC1 (with the presence of an unmodulated
carrier) such that the dc level at Pin 3 (DEMOD_DATA) is
equal to the voltage on the external reference pin VREF.
Two demodulation modes are supported. In one mode any
frequency offset due to reference drift or frequency offsets on
the incoming carrier are propagated to the output (referred to as
“Normal” demodulation). The other method is to use a feature
of the DECT system that enables a secondary compensation
circuit to track out frequency offsets (“S-field sampling,” which
is enabled by the pin SFS—active high together with the con-
VCC
VCCFigure 1.Functional Block Diagram
AD6411The block diagram shows the principle of operation of these two
modes together with the internal switch settings as shown in
Figure 2.
Table I.Supported Demodulation ModesAn important consideration in normal demodulation mode is
any drift after the initial setup of the VCO. One mechanism is
the Capacitance vs. Temperature coefficient of the external
varactor. This has a known characteristic which is compensated
by an internal reference voltage generation circuit.
UHF VCOA single UHF VCO oscillator is provided operating at one-half
the required frequency. Therefore, in transmit mode the
oscillator operates from (approximately) 940 MHz to 950 MHz,
and in receive mode the oscillator operates from (approxi-
mately) 884 MHz–895 MHz. This requires a switched resona-
tor design, and band switch control is provided by the AD6411.
A balanced oscillator configuration is used which has the advan-
tages of rejection of common-mode interference and noise, and
less coupling to and from other parts of the IC and radio.
Transmit FunctionsThe DECT transmit function is achieved by direct modulation
of the UHF VCO operating at half the final transmit output
frequency. An on-chip doubler converts this to the final carrier
frequency. In this mode the synthesizer is set to a high imped-
ance mode i.e., “fly-wheeled.” The drift is sufficiently low for
both single-slot and double-slot transmit operation.
Synthesizer and LO FunctionsA complete synthesizer is implemented on the IC that is capable
of generating all the required DECT channel allocations (in-
cluding the extended DECT bands). This synthesizer can use
reference frequencies of either 13.824 MHz or 10.368 MHz,
controlled by the RD bit in the control register.
Synthesizer ProgrammingThe required channels are programmed by setting the RD bit in
the control register to the correct value, then programming the
A and M Counters as shown below through the serial interface.
VCC
150nH
IF/110.592MHzFigure 2.PLL Demodulator Block Diagram
