AD5516ABC-1-AD5516ABC-3 Fast Delivery |IC PHOENIX CO.,LIMITED

AD5516ABC-3 ,16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment ModeGENERAL DESCRIPTIONHigh Integration: The AD5516 is a 16-channel, 12-bit voltage-output DAC. The 16- ..
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AD5532ABC-1 ,32-Channel Infinite Sample-and-HoldSPECIFICATIONSto 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range fromV + 2 V to V – ..
AD5532ABC-2 ,32-Channel Infinite Sample-and-Hold32-Channel InﬁniteaSample-and-HoldAD5533*
AD5532ABC-5 ,32-Channel Infinite Sample-and-HoldAPPLICATIONSThe device is operated with AV = 5 V ± 5%, DV = 2.7 V toCC CCLevel Setting5.25 V, V = – ..
AD5532ABC-5 ,32-Channel Infinite Sample-and-HoldSPECIFICATIONSto 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range fromV + 2 V to V – ..
AD9627BCPZ-125 , 12-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
AD9630AN ,Low Distortion 750 MHz Closed-Loop Buffer AmpSPECIFICATIONSOutput Offset Voltage +25

AD5516ABC-1-AD5516ABC-3
16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode
REV.0
16-Channel, 12-Bit Voltage-Output DAC
with 14-Bit Increment Mode
FUNCTIONAL BLOCK DIAGRAM
RFB0
RESET
BUSY
DACGND
AGND
DGND
DCEN
DVCCAVCCVDDVSS
VOUT0
RFB1
VOUT1
RFB14
VOUT14
RFB15
VOUT15
REF_IN
SCLKDINDOUTSYNC
FEATURES
High Integration:
16-Channel DAC in 12 mm � 12 mm LFBGA
14-Bit Resolution via Increment/Decrement Mode
Guaranteed Monotonic
Low Power, SPITM, QSPITM, MICROWIRETM, and DSP-
Compatible
3-Wire Serial Interface
Output Impedance 0.5 �
Output Voltage Range
�2.5 V (AD5516-1)
�5 V (AD5516-2)
�10 V (AD5516-3)
Asynchronous Reset-Facility (via RESET Pin)
Asynchronous Power-Down Facility (via PD Pin)
Daisy-Chain Mode
Temperature Range: –40�C to +85�C
APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Optical Networks
Industrial Control Systems
Data Acquisition
Low Cost I/O
GENERAL DESCRIPTION
The AD5516 is a 16-channel, 12-bit voltage-output DAC. The
selected DAC register is written to via the 3-wire serial interface.
DAC selection is accomplished via address bits A3–A0. 14-bit
resolution can be achieved by fine adjustment in Increment/
Decrement Mode (Mode 2). The serial interface operates at
clock rates up to 20 MHz and is compatible with standard SPI,
MICROWIRE, and DSP interface standards. The output volt-
age range is fixed at ±2.5 V (AD5516-1), ±5 V (AD5516-2),
and ±10 V (AD5516-3). Access to the feedback resistor in each
channel is provided via RFB0 to RFB15 pins.
The device is operated with AVCC = 5 V ± 5%, DVCC = 2.7 V to
5.25 V, VSS = –4.75 V to –12 V, and VDD = +4.75 V to +12 V
and requires a stable 3 V reference on REF_IN.
PRODUCT HIGHLIGHTS
1. Sixteen 12-bit DACs in one package, guaranteed monotonic
2. Available in a 74-lead LFBGA package with a body size of
12 mm � 12 mm
*. Patent No. 5,969,657; other patents pending
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
AD5516
VOLTAGE REFERENCE
DIGITAL INPUTS
DIGITAL OUTPUTS (BUSY, DOUT)
NOTESSee Terminology section.A Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
–SPECIFICATIONS
(VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC =
2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded.
All specifications TMIN to TMAX unless otherwise noted.)
AC CHARACTERISTICS
AD5516
(VDD = +4.75 V to +13.2 V, VSS = –4.75V to –13.2 V; AVCC = 4.75V to 5.25V; DVCC = 2.7V to 5.25V; AGND = DGND
= DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk AD5516-1
Digital Feedthrough
NOTESSee Terminology section.Guaranteed by design and characterization; not production tested.A version: Industrial temperature range –40°C to +85°C.Timed from the end of a write sequence.
Specifications subject to change without notice.
NOTESSee Timing Diagrams in Figures 1 and 2.Guaranteed by design and characterization; not production tested.All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.This is measured with the load circuit of Figure 3.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
(VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;
AGND = DGND = DACGND = 0 V. All specifications TMIN to TMAX unless otherwise noted.)
AD5516
SERIAL INTERFACE TIMING DIAGRAMS
Figure 1.Serial Interface Timing Diagram
Figure 2.Daisy-Chaining Timing Diagram
Figure 3.Load Circuit for DOUT Timing Specifications
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5516 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted.)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17 V
AVCC to AGND, DACGND . . . . . . . . . . . . . .–0.3 V to +7 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . .–0.3 V to DVCC +0.3 V
Digital Outputs to DGND . . . . . . . . .–0.3 V to DVCC +0.3 V
REF_IN to AGND, DACGND . . . . .–0.3 V to AVCC+ 0.3 V
VOUT 0–15 to AGND . . . . . . . . . . . .VSS – 0.3 V to VDD +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
RFB0–15 to AGND . . . . . . . . . . . . VSS – 0.3 V to VDD+0.3 V
Operating Temperature Range, Industrial . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ MAX) . . . . . . . . . . . . . . . . . . .150°C
74-Lead LFBGA Package, �JA Thermal Impedance . .41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
Time at Peak Temperature . . . . . . . . . . . . .10 sec to 40 sec
NOTESStresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
AD5516
PIN CONFIGURATION10987654321
TOP VIEW10987654321
PIN FUNCTION DESCRIPTIONS
VSS (1–2)
DACGND
REF_IN
VOUT (0–15)
RFB (0–15)
SYNC
74-LEAD LFBGA BALL CONFIGURATION
NC = Not Internally Connected
A10
A11
TERMINOLOGY
Integral Nonlinearity (INL)
This is a measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It is
expressed in LSBs.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of –1 LSB maximum ensures
monotonicity.
Bipolar Zero Error
Bipolar zero error is the deviation of the DAC output from the ideal
midscale of 0 V. It is measured with 10...00 loaded to the DAC.
It is expressed in LSBs.
Positive Full-Scale Error
This is the error in the DAC output voltage with all 1s loaded to
the DAC. Ideally the DAC output voltage, with all 1s loaded to the
DAC registers, should be 2.5 V – 1 LSB (AD5516-1), 5 V – 1 LSB
(AD5516-2), and 10 V – 1 LSB (AD5516-3). It is expressed in LSBs.
Negative Full-Scale Error
This is the error in the DAC output voltage with all 0s loaded to the
DAC. Ideally the DAC output voltage, with all 0s loaded to the
DAC registers, should be –2.5 V (AD5516-1), –5 V (AD5516-2),
and –10 V (AD5516-3). It is expressed in LSBs.
Output Temperature Coefficient
This is a measure of the change in analog output with changes in
temperature. It is expressed in ppm/°C of FSR.
DC Power Supply Rejection Ratio
DC power supply rejection ratio (PSRR) is a measure of the change
in analog output for a change in supply voltage (VDD and VSS).
It is expressed in dBs. VDD and VSS are varied ±5%.
DC Crosstalk
This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in mV.
Output Settling Time
This is the time taken from when the last data bit is clocked into
the DAC until the output has settled to within ±0.5 LSB of its
final value (see TPC 7).
Digital-to-Analog Glitch Impulse
This is the area of the glitch injected into the analog output when
the code in the DAC register changes state. It is specified as the
area of the glitch in nV-secs when the digital code is changed by
1 LSB at the major carry transition (011...11 to 100...00 or
100...00 to 011...11).
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC at
midscale while a full-scale code change (all 1s to all 0s and vice
versa) is being written to another DAC. It is expressed in nV-secs.
Analog Crosstalk
This is the area of the glitch transferred to the output (VOUT) of
one DAC due to a full-scale change in the output (VOUT) of
another DAC. The area of the glitch is expressed in nV-secs.
Digital Feedthrough
This is a measure of the impulse injected into the analog outputs
from the digital control inputs when the part is not being written
to, i.e., SYNC is high. It is specified in nV-secs and measured
with a worst-case change on the digital input pins, e.g., from all
0s to all 1s and vice versa.
Output Noise Spectral Density
This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per root Hertz).
It is measured in nV/(Hz)1/2.
PIN FUNCTION DESCRIPTIONS (continued)
DCEN
RESET
BUSY
NOTESInternal pull-down device on this logic input. Therefore it can be left floating and will default to a logic low condition.Internal pull-up device on this logic input. Therefore it can be left floating and will default to a logic high condition.
TPC 1. Typical DNL Plot
TPC 4. Bipolar Zero Error and
Full-Scale Error vs. Temperature
TPC 7.Full-Scale Settling Time
TPC 2.Typical INL Plot
TPC 5.VOUT vs. Temperature
TPC 8.Exiting Power-Down to
Full Scale
TPC 3.Typical INL Error and DNL
Error vs. Temperature
TPC 6.VOUT Source and Sink
Capability
TPC 9.Major Code Transition
Glitch Impulse
–Typical Performance CharacteristicsAD5516

Partno	Mfg	Dc	Qty	Available	Descript
AD5516ABC-1 \|AD5516ABC1	AD	N/a	16	avai	16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode
AD5516ABC-3 \|AD5516ABC3	ADI	N/a	200	avai	16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode