AD421BN ,Loop-Powered 4 mA to 20 mA DACfeatures a programmable alarm current capabil-with ±0.2% gain error.ity that allows the transmitter ..
AD421BR ,Loop-Powered 4 mA to 20 mA DACSPECIFICATIONS (V = +3 V to +5 V; REF IN = REF OUT2; T = T to T unless otherwise noted)CC A MIN MAX ..
AD45048AR ,Rail-to-Rail, High Output Current, Upstream ADSL Line DriverSPECIFICATIONS °VS = ±6 V or 12 V (@ TA = 25 C, G = +10, RL = 100 Ω, unless otherwise noted). Table ..
AD45048ARZ ,Rail-to-Rail Upstream ADSL Line DriverSPECIFICATIONS °VS = ±6 V or +12 V (@ TA = 25 C, G = +10, RL = 100 Ω, unless otherwise noted). Tabl ..
AD45048ARZ-REEL ,Rail-to-Rail Upstream ADSL Line Driverapplications. Fabricated with ADI’s high speed XFCB-HV (eXtra Fast Complementary Bipolar-High Volt ..
AD45048ARZ-REEL7 ,Rail-to-Rail Upstream ADSL Line DriverFEATURES PIN CONFIGURATION Dual op amp OUT1 1 8 +VSVoltage feedback –IN1 2 7 OUT2Wide supply range: ..
AD8602ARM-R2 ,DigiTrim™ Dual Rail-to-Rail Input and Output Amplifier with Very Low Offset Voltage and Wide BandwidthsCHARACTERISTICSOutput Voltage High V I = 1.0 mA 4.925 4.975 4.925 4.975 VOH LI = 10 mA 4.7 4.77 4.7 ..
AD8602ARM-REEL ,DigiTrim™ Dual Rail-to-Rail Input and Output Amplifier with Very Low Offset Voltage and Wide BandwidthsCHARACTERISTICSOutput Voltage High V I = 1.0 mA 2.92 2.95 2.92 2.95 VOH L–40°C ≤ T ≤ +125°C 2.88 2. ..
AD8602ARM-REEL ,DigiTrim™ Dual Rail-to-Rail Input and Output Amplifier with Very Low Offset Voltage and Wide BandwidthsCHARACTERISTICSOffset Voltage (AD8601/AD8602) V 0 V ≤ V ≤ 5 V 80 500 1,300 6,000 µVOS CM–40°C ≤ T ≤ ..
AD8602AR-REEL ,DigiTrim™ Dual Rail-to-Rail Input and Output Amplifier with Very Low Offset Voltage and Wide BandwidthsApplications for these amplifiers include audio amplification forAD8601, single, is available in th ..
AD8602ARZ-REEL , Precision CMOS, Single-Supply, Rail-to-Rail, Input/Output Wideband Operational Amplifiers
AD8602ARZ-REEL , Precision CMOS, Single-Supply, Rail-to-Rail, Input/Output Wideband Operational Amplifiers
AD421BN-AD421BR
Loop-Powered 4 mA to 20 mA DAC
FUNCTIONAL BLOCK DIAGRAM
REF IN
(+2.5V)
REF OUT1
(+1.25V)
REF OUT2
(+2.5V)LVVCC
DRIVE
COMP
BOOST
LOOP
RTNC2C3COM
LATCH
CLOCK
DATAREV. C
FEATURES
4 mA to 20mA Current Output
HART® Compatible
16-Bit Resolution and Monotonicity�0.01% Integral Nonlinearity
V or 3V Regulator Output
2.5V and 1.25V Precision Reference
750�A Quiescent Current max
Programmable Alarm Current Capability
Flexible High Speed Serial Interface
16-Lead SOIC and PDIP Packages
Loop-Powered
4 mA to 20mA DAC
PRODUCT HIGHLIGHTSThe AD421 is a single chip, high performance, low cost
solution for generating 4 mA to 20mA signals for smart
industrial control transmitters.The AD421’s regulated supply voltage can be used to power
any additional circuits in the transmitter. The regulated
output value is pin selectable as either +3V, +3.3V or +5V.The AD421’s on-chip references can provide a precision
reference voltage to other devices in the system. This refer-
ence voltage can be either +1.25V or +2.5V.The AD421 is fully compatible with standard HART cir-
cuitry or other similar FSK protocols.With the addition of a single discrete transistor, the AD421
can be operated from VCC + 2 V min to a maximum of the
breakdown voltage of the pass transistor.The AD421 converts the digital data to current with 16-bit
resolution and monotonicity. Full-scale settling time to0.1% typically occurs within 8ms.The AD421 features a programmable alarm current capabil-
ity that allows the transmitter to send out of range currents to
indicate a transducer fault.
HART is a registered trademark of the HART Communication
Foundation.
GENERAL DESCRIPTIONThe AD421 is a complete, loop-powered, digital to 4 mA tomA converter, designed to meet the needs of smart trans-
mitter manufacturers in the Industrial Control industry. It pro-
vides a high precision, fully integrated, low cost solution in a
compact 16-lead package. The AD421 is ideal for extending the
resolution of smart 4 mA to 20mA transmitters at very low cost.
The AD421 includes a selectable regulator that is used to power
itself and other devices in the transmitter. This regulator pro-
vides either a +5V, +3.3V or +3V regulated output voltage.
The part also contains +1.25V and +2.5V precision references.
The AD421 thus eliminates the need for a discrete regulator
and voltage reference. The only external components required
are a number of passive components and a pass transistor to
span large loop voltages.
The AD421 can be used with standard HART FSK protocol
communication circuitry without any degradation in specified
performance. The high speed serial interface is capable of oper-
ating at 10Mbps and allows for simple connection to com-
monly-used microprocessors and microcontrollers via a standard
three-wire serial interface.
The sigma-delta architecture of the DAC guarantees 16-bit
monotonicity while the integral nonlinearity for the AD421 is
±0.01%. The part provides a zero scale 4mA output current
with ±0.1% offset error and a 20mA full-scale output current
with ±0.2% gain error.
The AD421 is available in a 16-lead, 0.3 inch-wide, plastic DIP
and in a 16-lead, 0.3 inch-wide, SOIC package. The part is speci-
fied over the industrial temperature range of –40°C to +85°C.
DAC SPECIFICATIONSNOTES
1The DN25D is available from Supertex, Inc., 1350 Bordeaux Drive, Sunnyvale, CA 94089.Temperature range is –40°C to +85°C.
AD421–LOOP-POWERED SPECIFICATIONS
(Using DN25D1 as pass transistor as per Figure 3;
REF IN = REF OUT2; TA = TMIN to TMAX unless otherwise noted)
(VCC = +3V to +5V; REF IN = REF OUT2; TA = TMIN to TMAX unless otherwise noted)
TIMING CHARACTERISTICS1, 2, 3NOTESGuaranteed by characterization at initial product release, not production tested.See Figures 1 and 2.All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of (VIN + VIL)/2; tr and tf should not exceed 1µs on any digital
input.
Specifications subject to change without notice.
Figure 1.Serial Interface Waveforms (Normal Data Load)
Figure 2.Serial Interface Timing Diagram
(VCC = +3V to +5V, TA = TMIN to TMAX unless otherwise noted)
AD421
ORDERING GUIDE*N = Plastic DIP, R = SOIC.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
DRIVE, BOOST, COMP to COM . . . –0.5 V to VCC + 0.5 V
LOOP RTN to COM . . . . . . . . . . . . . . . . . . . –2 V to + 0.5 V
Digital Input Voltage to COM . . . . . . . –0.5 V to VCC + 0.5 V
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 670 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 116°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
DIP and SOIC
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONSAD421
Table I.FET Characteristicswhere VCC is the operating voltage of the AD421 and VLOOP is
the loop voltage.
The DN25D FET transistor from Supertex1 meets all the above
requirements for the FET. Other suitable transistors include
ND2020L and ND2410L, both from Siliconix.
There are a number of external components required to com-
pensate the regulator loop and ensure stable operation. The
capacitor from the VCC pin to the COM pin is required to
stabilize the regulator loop.
To provide additional compensation for the regulator loop, a
compensation capacitor of 0.01µF should be connected
between the COMP and DRIVE pins and an external circuit
of a 1kΩ resistor and a 1000pF capacitor in series should be
connected between DRIVE and COM to stabilize this feed-
back loop formed with the regulator op amp and the external
pass transistor.
DAC SectionThe AD421 contains a 16-bit sigma-delta DAC to convert the
digital information loaded to the input latch into a current. The
sigma-delta architecture is particularly useful for the relatively
low bandwidth requirements of the industrial control environ-
ment because of its inherent monotonicity at high resolution.
The AD421 guarantees monotonicity to the 16-bit level.
The sigma-delta DAC consists of a second order modulator
followed by a continuous time filter. The single bit stream from
the modulator controls a switched current source. This current
source is then filtered by three resistor-capacitor filter sections.
The resistors for each of the filter sections are on-chip while
the capacitors are external on the C1–C3 pins. To meet the
specified full-scale settling on the part, low dielectric absorption
capacitors (NPO) are required. Suitable values for these capacitors
are C1 = 0.01µF, C2 = 0.01µF, and C3 = 0.0033µF.
Current AmplifierThe DAC output current drives the second section, an opera-
tional amplifier and NPN transistor which acts as a current
amplifier to set the current flowing through the LOOP RTN
pin. Figure 4 shows the current amplifier section of the AD421.
An 80kΩ resistor connected between the DAC output and loop
return is used as a sampling resistor to determine current. The
base drive to the NPN transistor servos the voltage across theΩ resistor to equal the voltage across the 80kΩ resistor.
CIRCUIT DESCRIPTIONThe AD421 is designed for use in loop-powered 4–20mA smart
transmitter applications. A smart transmitter, as a remote in-
strument, controls its current output signal on the same pair of
wires from which it receives its power. The AD421 essentially
provides three primary functions in the smart transmitter. These
functions are a DAC function for converting the microprocessor/
microcontroller’s digital data to analog format, a current amp-
lifier which sets the current flowing in the loop and a voltage
regulator to provide a stable operating voltage from the loop
supply. The part also contains a high speed serial interface, two
buffered output references and a clock oscillator circuit. The
different sections of the AD421 are discussed in more detail
below.
Voltage RegulatorThe voltage regulator consists of an op amp, bandgap reference
and an external depletion mode FET pass transistor. This cir-
cuit is required to regulate the loop voltage that powers the
AD421 itself and the rest of the transmitter circuitry. Figure 3
shows the voltage regulator section of the AD421 plus the associ-
ated external circuitry for a VCC of 3.3 V.
Figure 3.AD421 Voltage Regulator Circuit to Provide
VCC = 3.3 V
The signal on the LV pin selects the voltage to which VCC
regulates by changing the gain of the resistor divider between
the op amp inverting input and the VCC pin. As the LV pin
varies between COM and VCC, the voltage from the regulator
loop varies between 3V and 5V nominal. With LV connected
to COM, the regulated voltage is 5V; with LV connected
through a 0.01µF capacitor to VCC, the regulated voltage is
3.3V while if LV is connected to VCC, the regulated voltage
is 3V.
The range of loop voltages that can be used by the configuration
shown in Figure 3 is determined by the FET breakdown and
saturation voltages. The external FET parameters such as Vgs
(off), IDSS and transconductance must be chosen so that the op
amp output on the DRIVE pin can control the FET operating
point while swinging in the range from VCC to COM.
The main characteristics for selecting the FET pass transistor
are as follows:
Reference SectionThe AD421 contains an on-chip 1.21V bandgap reference
which is used as part of the voltage regulator loop. A bandgap
reference is also used to generate two references voltages
which are available for use external to the AD421. Figure 5
shows the reference section of the AD421. The REF OUT1 pin
provides a buffered +1.25V reference voltage which can supply
up to 0.5mA of external current. The REF OUT2 pin provides
a +2.5V reference voltage which is also capable of providing
0.5mA of external current. To use the AD421 with its own
reference, simply connect the REF OUT2 pin to the REF IN
pin of the device. Alternatively, the part can be used with an
external reference by connecting the external reference between
REF IN and COM.
When REFOUT1 and REFOUT2 are used in application
circuits, external 4.7µF capacitors are required on the reference
pins to provide compensation and ensure stable operation of the
references. These capacitors can be omitted if the internal refer-
ences are not required.
Figure 5.Reference Section
REF OUT2 is sensed internally, and if more than 0.5mA is
drawn externally from this reference, the chip goes into a power
on reset state. In this state the sigma-delta DAC is disabled, the
internal oscillator is stopped and the input data latch is cleared.
REF OUT1 has limited current sinking capability. If REF
OUT1 is required to sink current, a resistive load of 100kΩ
to COM should be added in addition to the 4.7µF capacitor.
USING THE AD421The AD421 can be programmed for normal 4 mA to 20mA
operation or for alarm current operation. For normal operation,
the coding is 16-bit straight (natural) binary over an output
current range of 4mA to 20mA. For alarm current operation,
the coding is also straight binary but with 17bits of resolution
over twice the span, 0mA to 32mA, although the part should
not be programmed outside the range of 3.5mA to 24mA. To
determine whether data written to the part is normal 4 mA tomA data or alarm current data, the number of clock pulses
between two successive LATCH pulses are counted. If the num-
ber of pulses is 0–16 (modulo 32), it chooses normal mode; if it
is 17–31 (modulo 32), it chooses alarm current range.
4 mA to 20mA CodingTable II shows the ideal input-code-to-output-current relation-
Figure 4.Current Amplifier
The BOOST pin is normally tied to the VCC pin. As the DAC
input code varies from all zeros to full scale, the output current
from the NPN transistor and thus the total loop current varies
from 4mA to 20mA. With BOOST and VCC tied together, the
external FET (DN25D) has to supply the full range of loop
current (4mA to 20mA).
Digital InterfaceThe digital interface on the AD421 consists of just three wires:
DATA, CLOCK and LATCH. The interface connects directly
to the serial ports of commonly-used microcontrollers without
the need for any external glue logic. Data is loaded MSB first
into an input shift register on the rising edge of the CLOCK
signal and is transferred to the DAC latch on the rising edge of
the LATCH signal. The timing diagrams for the serial interface
are shown in Figure 1 and Figure 2.
The data to be loaded to the AD421’s input shift register takes
two forms; normal 4mA to 20mA data or alarm current data.
The first form is where the AD421 operates over its normalmA to 20mA output range with 16 bits of resolution between
these endpoints. The second form allows the user to program a
current value outside this range as an indication from the trans-
mitter than there is a problem with the transducer. The AD421
counts the number of clock pulses which it receives between
LATCH signals as a means of determining whether the data
clocked in is 4mA to 20mA data or alarm current data.
If there are 16 rising clock edges between successive LATCH
pulses, then the data being loaded to the input shift register is
assumed to be normal 4mA to 20mA data. On the rising edge
of the LATCH signal, the input shift register data is transferred
to the DAC latch in a 16-bit parallel transfer. In this case, the
16 bits of data in the DAC latch program the output current
between 4mA for all 0s and 20mA for all 1s (see Table II).
Data transferred to the AD421 should be MSB first.
If there are more than 16 clock pulses between successive
LATCH pulses, then the data being loaded to the input shift
register is assumed to be alarm current data. In this case, the
AD421 accepts 17 bits of data into its shift register. For situa-
tions where there are more than 17 clocks in the serial write
operation (for example, 24 clocks in a 3 × 8-bit transfer from the
serial port of a microcontroller) the AD421 simply accepts the
last 17 bits of the serial write operation. Data transferred in this
serial write operation is LSB last (i.e., the MSB is loaded on the
17th rising clock edge prior to the LATCH pulse). On the rising
edge of the LATCH signal, the input shift register data is trans-
ferred to the DAC latch in a 17-bit parallel transfer. In this
case, the 17 bits of data in the DAC latch program the output
