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AD260AND-1 |AD260AND1ADI N/a8avaiHigh Speed, Logic Isolator with Power Transformer
AD260AND-2 |AD260AND2ADIN/a6avaiHigh Speed, Logic Isolator with Power Transformer
AD260AND-3 |AD260AND3ADIN/a10avaiHigh Speed, Logic Isolator with Power Transformer
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AD260BND-2 |AD260BND2ADN/a40avaiHigh Speed, Logic Isolator with Power Transformer
AD260BND-3 |AD260BND3ADIN/a10avaiHigh Speed, Logic Isolator with Power Transformer
AD260BND-4 |AD260BND4ADIN/a16avaiHigh Speed, Logic Isolator with Power Transformer
AD260BND-5 |AD260BND5ADIN/a22avaiHigh Speed, Logic Isolator with Power Transformer


AD260BND-2 ,High Speed, Logic Isolator with Power TransformerSpecifications are subject to change without notice.REV. 0–2–AD260ABSOLUTE MAXIMUM RATINGS*Paramete ..
AD260BND-3 ,High Speed, Logic Isolator with Power TransformerCHARACTERISTICSThreshold VoltagePositive Transition (V ) +5 V dc = 4.5 V 2.0 2.7 3.15 VT+ SYS+5 V d ..
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AD260BND-5 ,High Speed, Logic Isolator with Power TransformerGENERAL DESCRIPTION17V p-p OUTDRIVEThe AD260 is designed using Analog Devices new IsoLogicPWRA14 9 ..
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AD260AND-1-AD260AND-2-AD260AND-3-AD260AND-4-AD260AND-5-AD260BND-2-AD260BND-3-AD260BND-4-AD260BND-5
High Speed, Logic Isolator with Power Transformer
REV.0
High Speed, Logic Isolator
with Power Transformer
FUNCTIONAL BLOCK DIAGRAM
FEATURES
IsoLogic™ Circuit Architecture
Isolation Test Voltage: To 3.5 kV rms
Five Isolated Logic Lines: Available in Six I/O Configurations
Logic Signal Bandwidth: 20 MHz (Min), 40 mbps (NRZ)
Isolated Power Transformer: 37 V p-p, 1.5 W Max
CMV Transient Immunity: 10 kV/ms Min
Waveform Edge Transmission Symmetry: 61 ns
Field and System Output Enable/Three-State Functions
Performance Rated Over –258C to +858C
UL1950, IEC950, EN60950 Certification, Pending
APPLICATIONS
PLC/DCS Analog Input and Output Cards
Communications Bus Isolation
General Data Acquisition Applications
IGBT Motor Drive Controls
High Speed Digital I/O Ports
GENERAL DESCRIPTION

The AD260 is designed using Analog Devices new IsoLogic
circuit architecture to isolate five digital control signals to/
from a microcontroller and its related field I/O components. Six
models allow all I/O combinations from five input lines to five
output lines, including combinations in between. Every AD260
effectively replaces up to five opto-isolators while also providing
the 1.5 W transformer for a 3.5 kV isolated dc-dc power supply
circuit.
Each line of the AD260 has a bandwidth of 20MHz (min) with
a propagation delay of only 14 ns, which allows for extremely
fast data transmission. Output waveform symmetry is maintained
to within –1 ns of the input so the AD260 can be used to accu-
rately isolate time-based PWM signals.
All field or system output pins of the AD260 can be set to a high
resistance three-state level by use of the two enable pins. A field
output three-stated offers a convenient method of presetting
logic levels at power-up by use of pull-up/down resistors. Sys-
tem side outputs being three-stated allows for easy multiplexing
of multiple AD260s.
The isolation barrier of the AD260 B Grade is 100% tested at
3.5 kV rms (system to field). The barrier design also provides
excellent common-mode transient immunity from 10 kV/ms
common-mode voltage excursions of field side terminals relative
to the system side, with no false output triggering on either side.
Each output is updated within nanoseconds by input logic tran-
sitions, the AD260 also has a continuous output update feature
that automatically updates each output based on the dc level of
the input. This guarantees the output is always valid 10ms after
a fault condition or after the power-up reset interval.
The AD260 also has an integral center tap transformer for gen-
erating isolated power. Typically driven by a 5 V push-pull drive
at the primary, it will generate a 37 V p-p output capable of
supplying up to 1.5 W. This can then be regulated to the de-
sired voltage, including –5 V dc for circuit components and
24 V for a 20 mA loop supply when needed.
PRODUCT HIGHLIGHTS
Six Isolated Logic Line I/O Configurations Available: The

AD260 is available in six pin-compatible versions of I/O con-
figurations to meet a wide variety of requirements.
Wide Bandwidth with Minimal Edge Error: The AD260 with

IsoLogic affords extremely fast isolation of logic signals due to itsMHz bandwidth and 14 ns propagation delay. It maintains a
waveform input-to-output edge transition error of typically less
than –1ns (total) for positive vs. negative transition.
3.5 kV rms Test Voltage Isolation Rating:
The AD260
B Grade is rated to operate at 1.25 kV rms and is 100% pro-
duction tested at 3.5 kV rms, using a standard ADI test method.
High Transient Immunity:
The AD260 rejects common-
mode transients slewing at up to 10 kV/ms without false trigger-
ing or damage to the device.
(Continued on page 6)
IsoLogic is a trademark of Analog Devices, Inc.
AD260–SPECIFICATIONS(Typical at TA = +258C, +5 V dcSYS, +5 V dcFLD, tRR = 50 ns max unless otherwise noted)
DYNAMIC RESPONSE
ISOLATION BARRIER RATING
TEMPERATURE RANGE
NOTESFor best performance, bypass +5 V dc supplies to com. at or near the device (0.01 mF). +5 V dc supplies are also internally bypassed with 0.05 mF.
2As the supply voltage is applied to either side of the AD260, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30ms after the point where
+5 V dcSYS & FLD passes above 3.3 V.
3“Operating” isolation voltage is derived from the Isolation Test Voltage in accordance with such methods as found in VDE-0883 wherein a device will be “hi-pot” tested at twice
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
ABSOLUTE MAXIMUM RATINGS*

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may effect device reliability.
I/O CONFIGURATIONS AVAILABLE

The AD260 is available in several configurations. The choice of
model is determined by the desired number of input vs. output
lines. All models have identical footprints with the power and
enable pins always being in the same locations.
PIN CONFIGURATION
ENABLESYS
+5VdcSYS
5V RTNSYS
DRVA
DRVCT
DRVB
PWRBFLD
PWRCTFLD
PWRAFLD
5V RTNFLD
+5VdcFLD
ENABLEFLD
ORDERING GUIDE
PIN FUNCTION DESCRIPTIONS

*Function of pin determined by model. Refer to Table I.
Caution: Use care in handling unit as contaminants on the bot-

tom side of the unit or the circuit card to which it is mounted will
lead to reduced breakdown voltage across the isolation barrier.
AD260
AD260BND-021
DRVADRVCTDRVB
+5VdcFLD
5V RTNFLD
ENABLEFLD
PWRAFLD
PWRCTFLD
PWRBFLD
5V RTNSYS
+5VdcSYS
ENABLESYS17
AD260BND-121
DRVADRVCTDRVB
+5VdcFLD
5V RTNFLD
ENABLEFLD
PWRAFLD
PWRCTFLD
PWRBFLD
5V RTNSYS
+5VdcSYS
ENABLESYS17
PIN CONFIGURATIONS
AD260BND-2
AD260BND-3
PIN CONFIGURATIONS
Table I.

*Pin function is the same on all models, as shown in the AD260BND-0 column.
AD260BND-421
DRVADRVCTDRVB
+5VdcFLD
5V RTNFLD
ENABLEFLD
PWRAFLD
PWRCTFLD
PWRBFLD
5V RTNSYS
+5VdcSYS
ENABLESYS17
AD260BND-5
AD260
tff
37%
63%OUTPUT
INPUT
POSITIVE GOING
HYSTERESIS
PROPAGATION DELAY
BUFFERDELAY LINE
SCHMITT
TRIGGER
OUTPUT
CAPACITANCEtrr = tff = 100V x CTOTAL OUTPUT CAPACITANCE

>0.5ns – NO LOAD
= 5.5ns INTO 50pF
INPUT
CAPACITANCE
TOTAL DELAY = (tPLH OR tPHL) = tPD + (trr OR tff) >13ns (NO LOAD), 18ns (50pF LOAD)
EFFECTIVE CIRCUIT MODEL FOR ONE ISOLATED LOGIC LINE

(Continued from page 1)
Integral Isolated Power: The AD260 includes an integral,

uncommitted and flexible 1 Watt power transformer for devel-
oping isolated field power sources.
Field and System Enable Functions:
Both the isolated and
nonisolated sides of the AD260 have ENABLE pins that three-
state all outputs. Upon reenabling these pins, all outputs are
updated to reflect the current input logic level.
CE Certifiable:
Simply by adding the external bypass capacitors
at the supply pins, the AD260 can attain CE certification in
most applications (to the EMC directive) and conformance to
the low voltage (safety) directive is assured by the EN60950
certification.
GENERAL ATTRIBUTES

The AD260 provides five HCMOS/ACMOS compatible isolated
logic lines with ‡ 10 kV/ms common-mode transient immunity.
The case design and pin arrangement provides greater than
18 mm spacing between field and system side conductors, pro-
viding CSA/IS and IEC creepage spacing consistent with 750 V
mains isolation.
The five unidirectional logic lines have six possible combina-
tions of “ins” and “outs,” or transmitter/receiver pairs; hence
there are six AD260 part configurations (see Table I).
Each 20 MHz logic line has a Schmidt trigger input and a three-
state output (on the other side of the isolation barrier) and 14 ns of
propagation delay. A single enable pin on either side of the
barrier causes all outputs on that side to go three-state and all
inputs (driven pins) to ignore their inputs and retain their last
known state.
Note: All unused logic inputs (1–5) should be tied either high or low,
but not left floating.
Edge “fidelity,” or the difference in propagation time for rising
and falling edges, is typically less than –1 ns.
Power consumption, unlike opto-isolators, is a function of operat-
ing frequency. Each logic line barrier driver requires about 160mA
per MHz and each receiver 40 mA per MHz plus, of course, 4 mA
total idle current (each side). The supply current diminishes
slightly with increasing temperature (about –0.03%/°C).
The total capacitance spanning the isolation barrier is less thanpF.
The minimum width of a pulse that can be accurately coupled
across the barrier is about 25 ns. Therefore the maximum
square-wave frequency of operation is 20 MHz.
Logic information is sent across the barrier as “set-hi/set-lo”
data that is derived from logic level transitions of the input. At
power-up or after a fault condition, an output might not repre-
sent the state of the respective channel input to the isolator. An
internal circuit operates in the background which interrogates all
inputs about every 5ms and in the absence of logic transitions,
sends appropriate “set-hi” or “set-lo” data across the barrier.
Recovery time from a fault condition or at power-up is thus
between 5 ms and 10 ms.
DATA
RECEIVER
OUTPUT
BUFFER
GATED
TRANSPARENT
LATCH
SCHMITT
TRIGGER
UPDATE CIRCUIT
3.5kV
ISOLATION
BARRIER
DATA IN
ENABLEENABLE
OUT
DATA
TRANSMITTER

Figure 1.Simplified Block Diagram
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