74VHC32M ,Quad 2-Input OR GateFeaturesThe VHC32 is an advanced high speed CMOS 2-Input OR
74VHC32M-74VHC32MTC-74VHC32MTCX-74VHC32MX-74VHC32N-74VHC32SJ-74VHC32SJX
Quad 2-Input OR Gate
74VHC32 Quad 2-Input OR Gate November 1992 Revised February 2005 74VHC32 Quad 2-Input OR Gate General Description Features The VHC32 is an advanced high speed CMOS 2-Input ORHigh Speed: Gate fabricated with silicon gate CMOS technology. It t 3.8 ns (typ) at V 5V PD CC achieves the high speed operation similar to equivalent Low Power Dissipation: Bipolar Schottky TTL while maintaining the CMOS low I 2 PA (Max) at T 25qC power dissipation. CC A The internal circuit is composed of 4 stages including bufferHigh Noise Immunity: V V 28% V (Min) NIH NIL CC output, which provide high noise immunity and stable out- Power down protection is provided on all inputs put. An input protection circuit ensures that 0V to 7V can be Low Noise: V 0.8V (Max) OLP applied to the input pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systemsPin and Function Compatible with 74HC32 and two supply systems such as battery back up. This cir- cuit prevents device destruction due to mismatched supply and input voltages. Ordering Code: Package Order Number Package Description Number 74VHC32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC32MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow (Note 1) 74VHC32SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC32MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC32MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide 74VHC32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbol Connection Diagram IEEE/IEC Truth Table AB O Pin Descriptions HHH LH H Pin Names Description HL H A , B Inputs n n LLL O Outputs n © 2005 DS011518
