74VHC174 ,HEX D-TYPE FLIP FLOP WITH CLEAR74VHC174HEX D-TYPE FLIP FLOP WITH CLEAR
74VHC174
HEX D-TYPE FLIP FLOP WITH CLEAR
1/14November 2004 HIGH SPEED:
fMAX = 175MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 4 μA (MAX.) at TA =25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (MAX.)
DESCRIPTIONThe 74VHC174 is an advanced high-speed
CMOS HEX D-TYPE FLIP FLOP WITH CLEAR
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS technology.
Information signals applied to D inputs are
transferred to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC174HEX D-TYPE FLIP FLOP WITH CLEAR
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 4
74VHC1742/14
Figure 2: Input Equivalent Circuit Table 2: Pin Description
Table 3: Truth Table X : Don’t Care
Figure 3: Logic Diagram This logic diagram has not to be used to estimate propagation delays
74VHC1743/14
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions 1) VIN from 30% to 70% of VCC
74VHC1744/14
Table 6: DC Specifications
74VHC1745/14
Table 7: AC Electrical Characteristics (Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
Table 8: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/6 (per
Flip-Flop)
74VHC1746/14
Table 9: Dynamic Switching Characteristics 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
Figure 4: Test Circuit CL =15/50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
74VHC1747/14
Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)
Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)
