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74VHC16244TTRSTN/a6000avai16-BIT BUS BUFFER WITH 3-STATE OUTPUTS (NON INVERTED)


74VHC16244TTR ,16-BIT BUS BUFFER WITH 3-STATE OUTPUTS (NON INVERTED)74VHC1624416-BIT BUS BUFFERWITH 3-STATE OUTPUTS (NON INVERTED)■ HIGH SPEED:t = 5.4 ns (TYP.) at V = ..
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74VHC16244TTR
16-BIT BUS BUFFER WITH 3-STATE OUTPUTS (NON INVERTED)
1/10February 2003 HIGH SPEED:
tPD= 5.4ns (TYP.)at VCC =5V LOW POWER DISSIPATION:CC =4 μA (MAX.)atTA =25°C HIGH NOISE IMMUNITY:NIH =VNIL= 28%VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH|=IOL =8 mA (MIN) BALANCED PROPAGATION DELAYS: PLH≅t PHL OPERATING VOLTAGE RANGE:
VCC(OPR)= 2Vto 5.5V PIN AND FUNCTION COMPATIBLE WITH SERIES 16244 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP= 0.9V (MAX.)
DESCRIPTION

The 74VHC16244is an advanced high-speed
CMOS 16-BIT BUS BUFFER (3-STATE) fabricat- with sub-micron silicon gate and double-layer
metal wiringC2 MOS tecnology.
Any nG output control governs four BUS
BUFFERS. Output Enable inputs (nG)tied
together give full16bit operation.
When nGis LOW, the outputs are enabled. Whenis HIGH, the output arein high impedance
state.
The deviceis designedto be used with 3-state
memory address drivers, etc.
Power down protectionis provided onall inputs
and0to 7V canbe acceptedon inputs withno re-
gardto the supply voltage. This device can be
usedto interface 5Vto 3V.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
74VHC16244

16-BIT BUS BUFFER
WITH 3-STATE OUTPUTS (NON INVERTED)
ORDER CODES
PIN CONNECTION
74VHC16244
2/10
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
: Don’t Care: High Impedance
IEC LOGIC SYMBOLS
74VHC16244
3/10
ABSOLUTE MAXIMUM RATINGS

AbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not implied
RECOMMENDED OPERATING CONDITIONS
VIN from 30%to 70%of VCC
74VHC16244
4/10 SPECIFICATIONS
74VHC16244
5/10 ELECTRICAL CHARACTERISTICS (Inputtr=tf =3ns)
(*) Voltage rangeis 3.3V± 0.3V
(**) Voltage rangeis 5.0V± 0.5V
Note1: Parameter guaranteedby design. tsoLH =|tpLHm -tpLHn|, tsoHL =|tpHLm -tpHLn|
CAPACITIVE CHARACTERISTICS
CPD isdefinedasthe valueofthe IC’s internal equivalent capacitance whichis calculatedfrom theoperating current consumption without
load. (Referto Test Circuit). Average operating currentcanbe obtainedbythe following equation. ICC(opr) =CPD xVCC xfIN +ICC/16(per
Latch)
74VHC16244
6/10
DYNAMIC SWITCHING CHARACTERISTICS
Worst case package. Max numberof outputs definedas(n). Data inputsare driven0Vto 5.0V, (n-1) outputs switching andone outputat GND. Max numberof data inputs(n) switching. (n-1) switching0Vto 5.0V. Inputs undertest switching: 5.0Vto threshold (VILD),0Vto threshold
(VIHD), f=1MHz.
TEST CIRCUIT
= 15/50pFor equivalent (includesjigand probe capacitance) =R1= 1KΩ or equivalent =ZOUTof pulse generator (typically 50Ω)
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