74VHC112MX ,Dual J-K Flip-Flops with Preset and ClearGeneral Descriptionand Q HIGH. The VHC112 is an advanced high speed CMOS deviceAn input protection ..
74VHC112N ,Dual J-K Flip-Flops with Preset and ClearGeneral Descriptionand Q HIGH. The VHC112 is an advanced high speed CMOS deviceAn input protection ..
74VHC112SJ ,Dual J-K Flip-Flops with Preset and ClearFeaturesgering occurs at a voltage level of the clock and is notdirectly related to transition time ..
74VHC123A ,Dual Retriggerable Monastable Multivibratorfeatures both a nega-tive, A, and a positive, B, transition triggered input, either of
74VHC123AMTC ,Dual Retriggerable Monastable MultivibratorGeneral Descriptionapplied to the input pins without regard to the supply volt-The VHC123A is an ad ..
74VHC123AMTCX ,Dual Retriggerable Monastable MultivibratorGeneral Descriptionapplied to the input pins without regard to the supply volt-The VHC123A is an ad ..
88CNQ060A ,60V 80A Schottky Common Cathode Diode in a D61-8 packageBulletin PD-20058 rev. B 01/0288CNQ060A SeriesSCHOTTKY RECTIFIER 80 AmpNew GenIII D-61 Packag ..
88CNQ060ASL ,60V 80A Schottky Common Cathode Diode in a D61-8-SL packageapplications are in switching power supplies, converters, freewaveformwheeling diodes, and reverse ..
88CNQ060ASM ,60V 80A Schottky Common Cathode Diode in a D61-8-SM packageFeaturesThe 88CNQ060A center tap Schottky rectifier module hasCharacteristics 88CNQ...A Units been ..
88E1040 , Alaska® Quad Gigabit Ethernet Transceivers
74VHC112M-74VHC112MTC-74VHC112MTCX-74VHC112MX-74VHC112N-74VHC112SJ
Dual J-K Flip-Flops with Preset and Clear
74VHC112 Dual J-K Flip-Flops with Preset and Clear September 1995 Revised April 1999 74VHC112 Dual J-K Flip-Flops with Preset and Clear Simultaneous LOW signals on PR and CLR force both Q General Description and Q HIGH. The VHC112 is an advanced high speed CMOS device An input protection circuit ensures that 0V to 7V can be fabricated with silicon gate CMOS technology. It achieves applied to the input pins without regard to the supply volt- the high-speed operation similar to equivalent Bipolar age. This device can be used to interface 5V to 3V systems Schottky TTL while maintaining the CMOS low power dissi- and two supply systems such as battery backup. This cir- pation. cuit prevents device destruction due to mismatched supply The VHC112 contains two independent, high-speed JK flip- and input voltages. flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig- Features gering occurs at a voltage level of the clock and is not directly related to transition time. The J and K inputs can � High speed: f = 200 MHz (typ) at V = 5.0V MAX CC change when the clock is in either state without affecting � Low power dissipation: I = 2 μA (max) at T = 25°C CC A the flip-flop, provided that they are in the desired state dur- � High noise immunity: V = V = 28% V (min) NIH NIL CC ing the recommended setup and hold times relative to the falling edge of the clock. The LOW signal on PR or CLR � Power down protection is provided on all inputs prevents clocking and forces Q and Q HIGH, respectively. � Pin and function compatible with 74HC112 Ordering Code: Order Number Package Number Package Description 74VHC112M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74VHC112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC112MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC112N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description J , J , K , K Data Inputs 1 2 1 2 CLK , CLK Clock Pulse Inputs (Active Falling Edge) 1 2 CLR , CLR Direct Clear Inputs (Active LOW) 1 2 PR , PR Direct Preset Inputs (Active LOW) 1 2 Q , Q , Q , Q Outputs 1 2 1 2 © 1999 DS012123.prf
