74VCXR162601MTX ,Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Ohm Series Resistors in the Outputsapplications such as memory address drivers,clock drivers, and bus transceivers/transmitters. Order ..
74VHC00 ,QUAD 2-INPUT NAND GATE74VHC00 74VHCT00Quad2-InputNANDGate#October199574VHC00 74VHCT00#Quad2-InputNANDGateGeneralDescripti ..
74VHC00FT ,74VHC CMOS logic IC seriesFeatures(1) High speed: t = 3.7 ns (typ.) at V = 5 Vpd CC(2) Low power dissipation: I = 2 µA (max) ..
74VHC00FT ,74VHC CMOS logic IC seriesabsolute maximum ratings, even briefly, lead to deterioration in IC performance or evendestruction. ..
74VHC00M ,QUAD 2-INPUT NAND GATEFeaturesThe VHC00 is an advanced high-speed CMOS 2-Input
74VCXR162601MTX
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Ohm Series Resistors in the Outputs
74VCXR162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the Outputs August 1998 Revised October 2004 74VCXR162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the Outputs General Description Features The VCXR162601, 18-bit universal bus transceiver, com-1.4V to 3.6V V supply operation CC bines D-type latches and D-type flip-flops to allow data flow 3.6V tolerant inputs and outputs in transparent, latched, and clocked modes. 26Ω series resistors on both the A and B Port outputs. Data flow in each direction is controlled by output-enable t (A to B, B to A) PD (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be con- 3.8 ns max for 3.0V to 3.6V V CC trolled by the clock-enable (CLKENAB and CLKENBA) Power-down HIGH impedance inputs and outputs inputs. For A-to-B data flow, the device operates in the Supports live insertion/withdrawal (Note 1) transparent mode when LEAB is HIGH. When LEAB is Static Drive (I /I ) LOW, the A data is latched if CLKAB is held at a HIGH-to- OH OL LOW logic level. If LEAB is LOW, the A bus data is stored ±12 mA @ 3.0V V CC in the latch/flip-flop on the LOW-to-HIGH transition of Uses patented noise/EMI reduction circuitry CLKAB. Output-enable OEAB is active-LOW. When OEAB Latchup performance exceeds 300 mA is HIGH, the outputs are in the high-impedance state. ESD performance: Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. Human body model > 2000V The 74VCXR162601 is designed for low voltage (1.4V to Machine model >200V 3.6V) V applications with I/O compatibility up to 3.6V. CC Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor; the minimum The VCXR162601 is also designed with 26Ω series resis- CC value of the resistor is determined by the current-sourcing capability of the tors on both the A and B Port outputs. This design reduces driver. line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. Ordering Code: Package Order Number Package Description Number 74VCXR162601MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2004 DS500171
