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74VCXHQ163245R-E from ST,ST, ST Microelectronics 103000pcs , Original Sealed Package , Alternate PN:74VCXHQ163245RE,16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR WITH BUS HOLD AND EMI NOISE CONTROL
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74VCXHQ163245R-E ST,ST N/a 103000
74VCXHQ163245R-E from STM, ST Microelectronics 10000pcs , Original Sealed Package , Alternate PN:74VCXHQ163245RE,16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR WITH BUS HOLD AND EMI NOISE CONTROL
74VCXHQ163245 16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVELTRANSLATOR WITH BUS HOLD AND EMI NOISE CONTROL  HIGH SPEED: t =6.0ns (MAX.) at T =85°C PD AV = 3.0V V = 2.3V; Bn to AnCCA CCB LOW POWER DISSIPATION:I = I = 20µ A(MAX.) at T =85°CCCA CCB A SYMMETRICAL OUTPUT IMPEDANCE:|I | = I = 2.6mA MIN at OHA OLAV = 3.0V; V = 1.65V or 2.3VTSSOP TFBGA µ TFBGACCA CCB|I | = I = 6mA (MIN at OHB OLBV = 2.3V or 3.0V; V = 1.65V)CCA CCBTable 1: Order Codes  BALANCED PROPAGATION DELAYS:t ≅ tPLH PHLPACKAGE T & R POWER DOWN PROTECTION ON INPUTS AND OUTPUTSTSSOP48 74VCXHQ163245TTR SERIES RESISTOR ON A SIDETFBGA54 74VCXHQ163245LBR LIMITED EMI NOISE: t ≅ t ≥ 4ns atµ TFBGA42 74VCXHQ163245TBRrA fAC =10pFL µ TFBGA42 (*) 74VCXHQ163245R-E OPERATING VOLTAGE RANGE:(*) Lead-Free Compliant.V (OPR) = 2.3V to 3.6V (1.2V Data CCARetention)isolated. The A-port interfaces with the 3V bus, theV (OPR) = 1.65V to 3.6V (1.2V Data CCBB-port with the 2.5V and 1.8V bus.Retention)All inputs are equipped with protection circuits PIN AND FUNCTION COMPATIBLE WITH against static discharge, giving them 2KV ESD74 SERIES 16245immunity and transient excess voltage. All floating BUS HOLD PROVIDED ON DATA INPUT bus terminals during High Z State don’t needBOTH SIDEexternal pull-up or pull-down resistor. LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17)Figure 1: Logic Diagram ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200VDESCRIPTIONThe 74VCXHQ163245 is a dual supply lowvoltage CMOS 16-BIT BUS TRANSCEIVERfabricated with sub-micron silicon gate and2five-layer metal wiring CMOS technology.Designed for use as an interface between a 3.3Vbus and a 2.5V or 1.8V bus in a mixed 3.3V/1.8V,3.3V/2.5V and 2.5V/1.8V supply systems, itachieves high speed operation while maintainingthe CMOS low power dissipation and limited riseand fall time (Low EMI).This IC is intended for two-way asynchronouscommunication between data buses and thedirection of data transmission is determined byn = 1, 2nDIR inputs. The enable inputs nG can be used todisable the device so that the buses are effectivelyRev. 3January 2005 1/1774VCXHQ163245Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description TFBGA54 PIN N° µ TFBGA42 PIN N° TSSOP PIN N° SYMBOL NAME AND FUNCTIONA3 B3 1 1DIR Directional ControlsJ3 F3 24 2DIR Directional ControlsA6, B5, B6, C5, A4, A5, A6, B5, 47, 46, 44, 43, 1A1 to 1A8 Data Inputs/Outputs C6, D5, D6, E5 B6, C5, C6, D5 41, 40, 38, 37E6, F5, F6, G5, D6, E5, E6, F5, 36, 35, 33, 32, 2A1 to 2A8 Data Inputs/Outputs G6, H5, H6, J6 F6,G4, G5, G6 30, 29, 27, 26A1, B2, B1, C2, A3, A2, A1, B2, 2, 3, 5, 6, 1B1 to 1B8 Data Inputs/Outputs C1, D2, D1, E2 B1, C2, C1, D2 8, 9, 11, 12E1, F2, F1, G2, D1, E2, E1, F2, 13, 14, 16, 17, 2B1 to 2B8 Data Inputs/Outputs G1, H2, H1, J1 F1,G3, G2, G1 19, 20, 22, 23J4 F4 25 2G Output Enable InputsA4 B4 48 1G Output Enable InputsD3, D4, E3, E4, C3, C4, E3, E4 4, 10, 15, 21, GND Ground (0V)F3, F4 28, 34, 39, 45A2, A5, B3, B4, - - NC No ConnectedH3, H4, J2, J5C4, G4 D4 42, 31 V Positive Supply VoltageCCAC3, G3 D3 7, 18 V Positive Supply VoltageCCB2/1774VCXHQ163245Figure 3: Pin Connection (top view for TSSOP, top through view for BGA) TSSOP TFBGAµ TFBGATable 3: Truth Table INPUTS FUNCTIONOUTPUTG DIR A BUS B BUSL L OUTPUT INPUT A = BL H INPUT OUTPUT B = AH X ZZZX=Don’t care; Z=High Impedance 3/1774VCXHQ163245Table 4:

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