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74VCX16841MTDFAIRCHILN/a13avaiLow Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
74VCX16841MTDXFAIN/a126avaiLow Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs


74VCX16841MTDX ,Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and OutputsFunctional DescriptionThe 74VCX16841 contains twenty D-type latches with D-type input changes. When ..
74VCX2245 ,Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs and 26-Ohm Series Resistors in B Outputsapplications such as memory address drivers, clock driv- Static Drive (I /I B outputs):OH OLers, an ..
74VCX2245MTC ,Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs and 26 Ohm Series Resistors in B Outputsapplications with I/O compatibility up to 3.6V. The

74VCX16841MTD-74VCX16841MTDX
Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
74VCX16841 Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs March 1998 Revised October 2004 74VCX16841 Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16841 contains twenty non-inverting latches with1.4V to 3.6V V supply operation CC 3-STATE outputs and is intended for bus oriented applica- 3.6V tolerant inputs and outputs tions. The device is byte controlled. The flip-flops appear t (D to O ) PD n n transparent to the data when the Latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time 3.0 ns max for 3.0V to 3.6V V CC is latched. Data appears on the bus when the Output Power-off high impedance inputs and outputs Enable (OE) is LOW. When OE is HIGH, the outputs are in Supports live insertion and withdrawal (Note 1) a high impedance state. Static Drive (I /I ) OH OL The 74VCX16841 is designed for low voltage (1.4V to 3.6V) V applications with I/O compatibility up to 3.6V. ±24 mA @ 3.0V V CC CC The 74VCX16841 is fabricated with an advanced CMOSUses patented noise/EMI reduction circuitry technology to achieve high speed operation while maintain-Latch-up performance exceeds 300 mA ing low CMOS power dissipation. ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor; the minimum CC value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74VCX16841MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) n LE Latch Enable Input n D –D Inputs 0 19 O –O Outputs 0 19 © 2004 DS500132
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