74VCX162835MTDX ,Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26 Ohm Series Resistors in OutputsFeaturesThe VCX162835 low voltage 18-bit universal bus driver
74VCX162835MTD-74VCX162835MTDX
Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26 Ohm Series Resistors in Outputs
74VCX162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in Outputs October 1998 Revised November 2000 74VCX162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in Outputs General Description Features The VCX162835 low voltage 18-bit universal bus driverCompatible with PC100 DIMM module specifications combines D-type latches and D-type flip-flops to allow data1.65V–3.6V V specifications provided CC flow in transparent, latched and clocked modes. 3.6V tolerant inputs and outputs Data flow is controlled by output-enable (OE), latch-enable 26Ω series resistors in outputs (LE), and clock (CLK) inputs. The device operates in t (CLK to O ) Transparent Mode when LE is held HIGH. The device PD n operates in clocked mode when LE is LOW and CLK is tog- 4.2ns max for 3.0V to 3.6V V CC gled. Data transfers from the Inputs (I ) to Outputs (O ) on n n 5.2ns max for 2.3V to 2.7V V CC a Positive Edge Transition of the Clock. When OE is LOW, 9.2ns max for 1.65V to 1.95V V CC the output data is enabled. When OE is HIGH the output Power-down high impedance inputs and outputs port is in a high impedance state. Supports live insertion/withdrawal (Note 1) The VCX162835 is designed with 26Ω series resistors in Static Drive (I /I ) the outputs. This design reduces noise in applications such OH OL ±12mA @ 3.0V V as memory address drivers, clock drivers, and bus trans- CC ceivers/transmitters. ±8 mA @ 2.3V V CC The 74VCX162835 is designed for low voltage (1.65V to ±3 mA @ 1.65V V CC 3.6V) V applications with I/O capability up to 3.6V. CCLatchup performance exceeds 300 mA The 74VCX162835 is fabricated with an advanced CMOSESD performance: technology to achieve high speed operation while maintain- Human body model > 2000V ing low CMOS power dissipation. Machine model >200V Note 1: To ensure the high impedance state during power up or power down, OE should be tied to V through a pulldown resistor; the minimum CC value of the resistor is determined by the current sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74VCX162835MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 DS500181
