74VCX162373MTDX ,Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and 26 Ohm Series Resistors in Outputsapplications with I/O compatibility up to 3.6V.CC
74VCX162373MTD-74VCX162373MTDX
Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and 26 Ohm Series Resistors in Outputs
74VCX162373 Low Voltage 16-Bit Transparent Latch January 2000 Revised November 2004 74VCX162373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in Outputs General Description The VCX162373 contains sixteen non-inverting latches Features with 3-STATE outputs and is intended for bus oriented 1.4V–3.6V V supply operation applications. The device is byte controlled. The flip-flops CC appear to be transparent to the data when the Latch enable 3.6V tolerant inputs and outputs (LE) is HIGH. When LE is LOW, the data that meets the 26Ω series resistors in outputs setup time is latched. Data appears on the bus when the t (I to O ) Output Enable (OE) is LOW. When OE is HIGH, the out- PD n n puts are in a high impedance state. 3.3 ns max for 3.0V to 3.6V V CC The VCX162373 is also designed with 26Ω resistors in the Power-off high impedance inputs and outputs outputs. This design reduces line noise in applications Support live insertion and withdrawal (Note 1) such as memory address drivers, clock drivers and bus Static Drive (I /I ) transceivers/transmitters. OH OL ±12 mA @ 3.0V V The 74VCX162373 is designed for low voltage (1.4V to CC 3.6V) V applications with I/O compatibility up to 3.6V. CCUses patented noise/EMI reduction circuitry The 74VCX162373 is fabricated with an advanced CMOSLatch-up performance exceeds 300 mA technology to achieve high speed operation while maintain- ESD performance: ing low CMOS power dissipation. Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor; the minimum CC value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Package Ordering Number Package Description Number 74VCX162373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) n LE Latch Enable Input n I –I Inputs 0 15 O –O Outputs 0 15 © 2004 DS500236
