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74V2T126STRSTN/a6300avaiDUAL BUS BUFFER (3-STATE)


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74V2T126STR
DUAL BUS BUFFER (3-STATE)
1/10December 2001 HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 1μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH| = IOL = 8mA (MIN) BALANCED PROPAGATION DELAYS:PLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 4.5V to 5.5V IMPROVED LATCH-UP IMMUNITY
DESCRIPTION

The 74V2T126 is an advanced high-speed CMOS
DUAL BUS BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
tecnology.
3-STATE control input nG has to be set LOW to
place the output into the high impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 3V to 5V systems
and it is ideal for portable applications like
personal digital assistant, camcorder and all
battery-powered equipment.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
74V2T126

DUAL BUS BUFFER (3-STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PRELIMINARY DATA
74V2T126
2/10
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE

X: "H" or "L"
Z: High Impedance
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS

1) VIN from 0.8V to 2V
74V2T126
3/10
DC SPECIFICATION
AC ELECTRICAL CHARACTERISTICS (Input t
r = tf = 3ns)
(*) Voltage range is 5.0V ± 0.5V
74V2T126
4/10
CAPACITIVE CHARACTERISTICS

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2
TEST CIRCUIT TEST CIRCUIT

CL =15/50pF or equivalent (includes jig and probe capacitance)
R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74V2T126
5/10
WAVEFORM 1 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
74V2T126
6/10
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