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74V1G80CTR-74V1G80STR
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
1/10July 2001 HIGH SPEED:
fMAX = 180MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 1μA(MAX.) at TA =25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH| = IOL = 8mA (MIN) at VCC = 4.5V BALANCED PROPAGATION DELAYS:PLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74V1G80 is an advanced high-speed CMOS
SINGLE POSITIVE EDGE TRIGGERED D-TYPE
FLIP-FLOP WITH INVERTED OUTPUT
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS technology. it is
designed to operate from 2V to 5.5V, making this
device ideal for portable applications.
This D-Type flip-flop is controlled by a clock input
(CK). On the positive transition of the clock, the Q
output will be set to the logic inverted state that
was setup at the D input.
Following the hold time interval, data at the D input
can be changed without affecting the level at the
output. Power down protection is provided on
input and 0 to 7V can be accepted on input with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
It’s available in the commercial temperature
range. All inputs and output are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
74V1G80SINGLE POSITIVE EDGE TRIGGERED
D-TYPE FLIP-FLOP
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74V1G802/10
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 30% to 70% of VCC
74V1G803/10
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
74V1G804/10
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
TEST CIRCUIT CL = 15/50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
74V1G805/10
WAVEFORM: PROPAGATION DELAY, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
