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74V1G70CTRSTN/a6000avaiSINGLE BUFFER


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74V1G70CTR
SINGLE BUFFER
1/9July 2001 HIGH SPEED: tPD = 3.6ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 1μA(MAX.) at TA =25°C HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUT SYMMETRICAL OUTPUT IMPEDANCE:OH| = IOL = 8mA (MIN) at VCC = 4.5V BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V IMPROVED LATCH-UP IMMUNITY
DESCRIPTION

The 74V1G70 is an advanced high-speed CMOS
SINGLE BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
technology.
The internal circuit is composed of 2 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on input and 0
to 7V can be accepted on input with no regard to
the supply voltage. This device can be used to
interface 5V to 3V.
74V1G70

SINGLE BUFFER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74V1G70
2/9
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS

1) VIN from 30% to 70% of VCC
74V1G70
3/9
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (Input t
r = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
CAPACITIVE CHARACTERISTICS

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
74V1G70
4/9
TEST CIRCUIT

CL =15/50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAY (f=1MHz; 50% duty cycle)


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