74LVX373MTR ,LOW VOLTAGE OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVX373TTR ,LOW VOLTAGE OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTSapplications.All inputs and outputs are equipped withThis 8 bit D-Type latch is controlled by a lat ..
74LVX374 ,Low Voltage Octal D-Type Flip-Flop with 3-STATE OutputsFunctional DescriptionThe LVX374 consists of eight edge-triggered flip-flops with With the Output E ..
74LVX374 ,Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
74LVX374MTC ,Low Voltage Octal D-Type Flip-Flop with 3-STATE OutputsFeaturesThe LVX374 is a high-speed, low-power octal D-type flip-
74LVX373MTR-74LVX373TTR
Low Voltage Octal Transparent Latch with 3-STATE Outputs
1/10July 2001 HIGH SPEED:
tPD=5.8ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: IL = 0.8V, VIH = 2V at VCC =3V LOW POWER DISSIPATION:CC = 4 μA (MAX.) at TA =25°C LOW NOISE:
VOLP = 0.3V (TYP .) at VCC =3.3V SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4 mA (MIN) at VCC =3V BALANCED PROPAGATION DELAYS:PLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74LVX373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX373LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LVX3732/10
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
Z : High Impedance
* : Q Outputs are Latched at the time when the LE INPUT is taken low logic level
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74LVX3733/10
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2.0V
DC SPECIFICATIONS
74LVX3734/10
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
74LVX3735/10
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
TEST CIRCUIT CL =15/50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74LVX3736/10
WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
