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74LVX112M-74LVX112MTC-74LVX112MX Fast Delivery,Good Price
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74LVX112MFSCN/a3696avaiLow Voltage Dual J-K Flip-Flops with Preset and Clear
74LVX112MTCFAIRCHILN/a48avaiLow Voltage Dual J-K Flip-Flops with Preset and Clear
74LVX112MXFAIRCHILN/a5000avaiLow Voltage Dual J-K Flip-Flops with Preset and Clear


74LVX112MX ,Low Voltage Dual J-K Flip-Flops with Preset and ClearGeneral Descriptionare in the desired state during the recommended setup andThe LVX112 is a dual J- ..
74LVX125 ,Low Voltage Quad Buffer with 3-STATE OutputsFeaturesThe LVX125 contains four independent non-inverting buff- Input voltage level translation f ..
74LVX125MTC ,Low Voltage Quad Buffer with 3-STATE OutputsFeaturesThe LVX125 contains four independent non-inverting buff-

74LVX112M-74LVX112MTC-74LVX112MX
Low Voltage Dual J-K Flip-Flops with Preset and Clear
74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear October 1996 Revised December 2003 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear either state without affecting the flip-flop, provided that they General Description are in the desired state during the recommended setup and The LVX112 is a dual J-K Flip-Flop where each flip-flop has hold times relative to the falling edge of the clock. independent inputs (J, K, PRESET, CLEAR, and CLOCK) The inputs tolerate voltages up to 7V allowing the interface and outputs (Q, Q). These devices are edge sensitive and of 5V systems to 3V systems. change states synchronously on the negative going transi- tion of the clock pulse. Triggering occurs at a voltage level Features of the clock and is not directly related to the transition time. Clear and Preset are independent of the clock and areInput voltage level translation from 5V–3V accomplished by a low logic level on the corresponding Ideal for low power/low noise 3.3V applications input. The J and K inputs can change when the clock is in Ordering Code: Order Number Package Number Package Description 74LVX112M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX112MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description J , J , K , K Data Inputs 1 2 1 2 CLK , CLK Clock Pulse Inputs (Active Falling edge) 1 2 CLR , CLR Direct Clear Inputs (Active LOW) 1 2 PR , PR Direct Preset Inputs (Active LOW) 1 2 Q , Q , Q , Q 1 2 1 2 © 2003 DS012158
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